Fix codegen missing submodule name mangling

src/codegen/shared.rs

@@ -5,17 +5,6 @@ use std::borrow::Cow;
 use crate::{instantiation::RealWire, linker::get_builtin_type, TypeUUID};
 
 
-pub fn mangle(str: &str) -> String {
-    let mut result = String::with_capacity(str.len());
-    for c in str.chars() {
-        if c.is_whitespace() || c == ':' {
-            continue;
-        }
-        result.push(if c.is_alphanumeric() { c } else { '_' });
-    }
-    result
-}
-
 pub fn get_type_name_size(id: TypeUUID) -> u64 {
     if id == get_builtin_type("int") {
         32 // TODO concrete int sizes

src/codegen/system_verilog.rs

@@ -183,7 +183,7 @@ impl<'g> CodeGenerationContext<'g> {
         write!(
             self.program_text,
             "module {}(\n\tinput {clk_name}",
-            mangle(&self.instance.name)
+            &self.instance.mangled_name
         )
         .unwrap();
         for (_id, port) in self.instance.interface_ports.iter_valids() {
@@ -306,7 +306,7 @@ impl<'g> CodeGenerationContext<'g> {
             if sm_md.link_info.is_extern == IsExtern::Extern {
                 self.write_template_args(&sm_md.link_info, &sm.template_args);
             } else {
-                self.program_text.write_str(&sm_inst.name).unwrap();
+                self.program_text.write_str(&sm_inst.mangled_name).unwrap();
             };
             let sm_name = &sm.name;
             let submodule_clk_name = sm_md.get_clock_name();

src/codegen/vhdl.rs

@@ -53,10 +53,6 @@ fn typ_to_declaration(mut typ: &ConcreteType) -> String {
 }
 
 impl<'g, 'out, Stream: std::fmt::Write> CodeGenerationContext<'g, 'out, Stream> {
-    fn instance_name(&self) -> String {
-        mangle(&self.instance.name)
-    }
-
     fn write_vhdl_code(&mut self) {
         match self.md.link_info.is_extern {
             IsExtern::Normal => {
@@ -82,7 +78,7 @@ impl<'g, 'out, Stream: std::fmt::Write> CodeGenerationContext<'g, 'out, Stream>
 
     fn write_entity(&mut self, commented_out: bool) {
         let comment_text = if commented_out { "-- " } else { "" };
-        let instance_name = self.instance_name();
+        let instance_name = &self.instance.name;
 
         let mut it = self.instance.interface_ports.iter_valids().peekable();
         let end = if it.peek().is_some() { ";" } else { "" };
@@ -115,7 +111,7 @@ impl<'g, 'out, Stream: std::fmt::Write> CodeGenerationContext<'g, 'out, Stream>
     }
 
     fn write_architecture(&mut self) {
-        let instance_name = self.instance_name();
+        let instance_name = &self.instance.name;
         writeln!(
             &mut self.program_text,
             "architecture Behavioral of {instance_name} is"

src/instantiation/mod.rs

@@ -157,6 +157,8 @@ pub struct InstantiatedPort {
 pub struct InstantiatedModule {
     /// Unique name involving all template arguments
     pub name: String,
+    /// Used in code generation. Only contains characters allowed in SV and VHDL
+    pub mangled_name: String,
     pub errors: ErrorStore,
     /// This matches the ports in [Module::ports]. Ports are not `None` when they are not part of this instantiation.
     pub interface_ports: FlatAlloc<Option<InstantiatedPort>, PortIDMarker>,
@@ -332,9 +334,22 @@ struct InstantiationContext<'fl, 'l> {
     linker: &'l Linker,
 }
 
+/// Mangle the module name for use in code generation
+fn mangle_name(str: &str) -> String {
+    let mut result = String::with_capacity(str.len());
+    for c in str.chars() {
+        if c.is_whitespace() || c == ':' {
+            continue;
+        }
+        result.push(if c.is_alphanumeric() { c } else { '_' });
+    }
+    result
+}
+
 impl<'fl, 'l> InstantiationContext<'fl, 'l> {
     fn extract(self) -> InstantiatedModule {
         InstantiatedModule {
+            mangled_name: mangle_name(&self.name),
             name: self.name,
             wires: self.wires,
             submodules: self.submodules,