Add specified latency support to latency counting

Introduced bug that latency counting doesn't reach constants in first_bit_idx_6

README.md

@@ -76,8 +76,10 @@ The main goals of the language are roughly listed below:
 - [x] Net-positive latency cycles error
 - [x] Disjoint nodes error
 - [x] Indeterminable port latency
-- [ ] Latency Counting uses latency specifiers
-- [ ] Latency for output-only modules
+- [x] Latency Counting uses latency specifiers
+- [x] Latency for output-only modules
+- [ ] Latency Counting is invariant across arbitrary algorithm starting nodes
+- [ ] Latency Counting for "disjoint Input-Output blocks"
 - [ ] Integrate into Verilog generation
 - [ ] Negative Registers
 - [ ] Latency Cuts

multiply_add.sus

@@ -434,35 +434,51 @@ module permute24 : bool[128] mbf, bool[24] valid_permutes, bool start -> bool[12
 
 
 
+module test_single_wire : int a -> int o {
+	o = a;
+}
+
 module disjoint_ports : int a, int b, int c -> int result {
 	reg result = a + b;
 	// don't touch c
 }
 
 module undeteriminable_input_latency : int a, int b -> int x, int y {
 	reg int a_d = a;
-    reg int t = a_d + b;
-    reg reg reg int a_ddd = a;
-    x = t + a_ddd;
+    int t = a_d + b;
+    reg reg reg int a_dd = a;
+	reg int t_d = t;
+    x = t_d + a_dd;
     y = t;
 }
 
 module determinable_input_latency : int a, int b -> int x, int y {
 	reg int a_d = a;
-    reg int t = a_d + b;
-    reg reg int a_ddd = a;
-    x = t + a_ddd;
+    int t = a_d + b;
+    reg reg int a_dd = a;
+	reg int t_d = t;
+    x = t_d + a_dd;
     y = t;
 }
 
 module specified_input_latency : int a'0, int b'1 -> int x, int y {
 	reg int a_d = a;
-    reg int t = a_d + b;
-    reg reg reg int a_ddd = a;
-    x = t + a_ddd;
+    int t = a_d + b;
+    reg reg reg int a_dd = a;
+	reg int t_d = t;
+    x = t_d + a_dd;
     y = t;
 }
 
+// This module is a copy of ::undeteriminable_input_latency, but it doesn't have an error, because we just assume the latency of the inner nodes to be the earliest possible. 
+module determinable_because_no_input_output_ports : int a -> int x {
+	reg int a_d = a;
+    int t = a_d;
+    reg reg reg int a_dd = a;
+	reg int t_d = t;
+    x = t_d + a_dd;
+}
+
 module bad_cycle : int a -> int r {
 	state int test;
 	initial test = 0;
@@ -482,3 +498,30 @@ module good_cycle : int a -> int r {
 
 	r = new_test;
 }
+
+module input_only : int i -> {
+	state int loop;
+	initial loop = 0;
+	loop = loop + i;
+}
+
+module multiple_inputs_only : int i, int i2 -> {
+	state int loop;
+	initial loop = 0;
+	loop = loop + i + i2;
+}
+
+module output_only : -> int o {
+	state int loop;
+	initial loop = 0;
+	loop = loop + 1;
+	reg o = loop;
+}
+
+module multiple_outputs_only : -> int o, int o2 {
+	state int loop;
+	initial loop = 0;
+	loop = loop + 1;
+	reg o = loop;
+	reg reg o2 = loop;
+}

src/dev_aid/lsp.rs

@@ -12,7 +12,7 @@ use crate::{
     dev_aid::syntax_highlighting::create_token_ide_info, 
     errors::{CompileError, ErrorCollector, ErrorLevel}, 
     flattening::FlatID, 
-    instantiation::{SubModuleOrWire, LATENCY_UNSET}, 
+    instantiation::{SubModuleOrWire, CALCULATE_LATENCY_LATER}, 
     linker::{FileData, FileUUID, FileUUIDMarker, Linker, LocationInfo}, 
     parser::perform_full_semantic_parse, 
     tokenizer::{CharLine, TokenizeResult}
@@ -327,7 +327,7 @@ fn gather_hover_infos(md: &Module, id: FlatID, is_generative : bool, file_cache:
                 if wire.original_wire != id {continue}
                 let typ_str = wire.typ.to_string(&file_cache.linker.types);
                 let name_str = &wire.name;
-                let latency_str = if wire.absolute_latency != LATENCY_UNSET {
+                let latency_str = if wire.absolute_latency != CALCULATE_LATENCY_LATER {
                     format!("{}", wire.absolute_latency)
                 } else {
                     "?".to_owned()