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This collection of tools is intended for simulating SEU errors in Xilinx FPGAs. It is fully automated system, which randomly places errors into content of LUTs. It uses real hardware (for now Spartan3 is supported and tested) and partial reconfiguration techniques.

Please visit Wiki for more details.

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Set of scripts to simulate SEU faults in Xilinx FPGAs including Spartan3

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