Fix USB-C downstream port programming.

We have to send an explicit SourceVbusDefaultVoltage command to the FUSB307 to enable the downstream port power controller. Once this is done, the board will advertise downstream power depending on the amount of current available from the upstream port.
oskirby · Jul 14, 2020 · 1e0b711 · 1e0b711
1 parent 00ae5c9
commit 1e0b711
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diff --git a/boards/logicbone_ecp5/Makefile b/boards/logicbone_ecp5/Makefile
@@ -39,6 +39,7 @@ PACKAGE = CABGA381
 BOOTADDR = 0x100000 # User image starts at 1MB
 
 all: $(PROJTOP).bit $(PROJTOP).hex $(PROJTOP).svf
+bootloader: $(PROJTOP).bit
 
 synth: $(PROJTOP).json
 
@@ -60,8 +61,11 @@ $(PROJTOP).json: $(SRC)
 prog: $(PROJTOP).svf
 	openocd -f logicbone-jlink.cfg -c "transport select jtag; init; svf $<; exit"
 
+dfu: $(PROJTOP).bit
+	dfu-util -d 1d50:615d -a2 -D $<
+
 clean:
 	rm -f $(PROJTOP).json $(PROJTOP).svf $(PROJTOP).bit $(PROJTOP)_out.config $(PROJTOP).hex
 
 .SECONDARY:
-.PHONY: all synth prog clean gui
+.PHONY: all bitstream synth prog dfu clean gui
diff --git a/boards/logicbone_ecp5/README.md b/boards/logicbone_ecp5/README.md
@@ -0,0 +1,27 @@
+TinyDFU for the Logicbone ECP5
+==============================
+This port allows the DFU bootloader to operate on a Logicbone ECP5 board.
+
+At power-on, the `BOOT` is checked to see if the board should remain in
+bootloader mode, or if the board should boot into the user image after a
+short timeout.
+
+When the bootloader is running, but idle, LED0 will blink at a little more
+than 1Hz. When the bootloader is running and a `DFU_UPLOAD` or `DFU_DNLOAD`
+operation is inprogress, the LEDs will cycle back and forth.
+
+Building
+========
+A `Makefile` has been provided that allows you to build and program the DFU
+bootloader. It supports the following make targets:
+
+| Target         | Description                                                 |
+|:---------------|:------------------------------------------------------------|
+| `bootloader`   | Build the bootloader bitstream for an Logicbone ECP5        |
+| `prog`         | Program the bootloader into the FPGA using OpenOCD.         |
+| `dfu`          | Program the bootloader into the flash using dfu-util.       |
+| `clean`        | Delete any files generated by the build.                    |
+
+The FPGA device can be overridden by specifying a `DEVICE=--um5g-45k` argument
+to make if you have a Logicbone with a different FPGA size. The default value
+is `--um5g-45k`, which builds for an LFE5UM5G-45F.
diff --git a/boards/logicbone_ecp5/i2c_bringup.v b/boards/logicbone_ecp5/i2c_bringup.v
@@ -127,9 +127,8 @@ localparam I2C_SEQ_WRITE_DFP_GPIO1        = 19'b0000000000000100000;
 localparam I2C_SEQ_WRITE_DFP_GPIO2        = 19'b0000000000001000000;
 localparam I2C_SEQ_WRITE_DFP_ROLECTL      = 19'b0000000000010000000;
 localparam I2C_SEQ_COMMAND_DFP_SINK       = 19'b0000000000100000000;
-localparam I2C_SEQ_READ_DFP_PWRSTAT       = 19'b0000000001000000000;
-localparam I2C_SEQ_DONE                   = 19'b0000000010000000000;
-localparam I2C_SEQ_FAIL                   = 19'b0000000100000000000;
+localparam I2C_SEQ_DONE                   = 19'b0000000001000000000;
+localparam I2C_SEQ_FAIL                   = 19'b0000000010000000000;
 reg [17:0]                 i2c_seq_state;
 reg [17:0]                 next_i2c_seq_state;
 
@@ -267,19 +266,7 @@ always @(*) begin
     i2c_address         = FUSB307_BUS_ADDR;
     i2c_write_length    = 2;
     i2c_read_length     = 0;
-    i2c_write_data      = {16'b0, 8'h99, FUSB307_REG_COMMAND};
-    //i2c_write_data      = {16'b0, 8'h61, FUSB307_REG_PWRCTRL};
-
-    next_i2c_start = ~i2c_busy;
-    if (i2c_busy_end) next_i2c_seq_state = I2C_SEQ_READ_DFP_PWRSTAT;
-  end
-
-  // Debug - check if we successfully enabled the DFP port.
-  I2C_SEQ_READ_DFP_PWRSTAT: begin
-    i2c_address         = FUSB307_BUS_ADDR;
-    i2c_write_length    = 1;
-    i2c_read_length     = 3;
-    i2c_write_data      = {24'b0, FUSB307_REG_CCSTAT};
+    i2c_write_data      = {16'b0, 8'h77, FUSB307_REG_COMMAND};
 
     next_i2c_start = ~i2c_busy;
     if (i2c_busy_end) begin
@@ -289,6 +276,7 @@ always @(*) begin
   end
 
   I2C_SEQ_DONE: begin
+    next_i2c_seq_state = I2C_SEQ_DONE;
   end
 
   endcase

diff --git a/boards/logicbone_ecp5/logicbone_ecp5.v b/boards/logicbone_ecp5/logicbone_ecp5.v
@@ -20,10 +20,13 @@ module logicbone_ecp5 (
     // i2c interface
     inout        i2c_scl,
     inout        i2c_sda,
-                       
+
     output [15:0] debug
 );
 
+wire i2c_bringup_done;
+wire i2c_bringup_fail;
+
 // Use an ecppll generated pll
 wire clk_48mhz;
 wire clk_locked;
@@ -75,7 +78,7 @@ always @(posedge clk) begin
     if (pwr_button == 1'b0) user_bootmode <= 1'b1;
     if (usb_reset && dfu_state == 8'h01) user_bootmode <= 1'b0;
 end
-BB pin_resetn( .I( 1'b0 ), .T( user_bootmode || reset_delay ), .O( ), .B( resetn ) );
+BB pin_resetn( .I( 1'b0 ), .T( user_bootmode || reset_delay || ~i2c_bringup_done), .O( ), .B( resetn ) );
 
 wire usb_p_tx;
 wire usb_n_tx;
@@ -87,7 +90,7 @@ wire usb_tx_en;
 usb_dfu_core dfu (
   .clk_48mhz  (clk_48mhz),
   .clk        (clk),
-  .reset      (~user_bootmode),
+  .reset      (usb_reset || ~user_bootmode),
 
   // USB signals
   .usb_p_tx( usb_p_tx ),
@@ -128,9 +131,6 @@ BB pin_usb_pull( .I( 1'b1 ), .T( ~user_bootmode ), .O( ), .B( usb_ufp_pull ) );
 //////////////////////////
 // I2C Board Setup
 //////////////////////////
-wire i2c_bringup_done;
-wire i2c_bringup_fail;
-
 wire i2c_scl_in;
 wire i2c_scl_drive_n;
 wire i2c_sda_in;