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    296 repositories

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      Tcl
      •
      Other
      •14•5•0•6•Updated Jan 26, 2025Jan 26, 2025

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •34•40•7•4•Updated Jan 26, 2025Jan 26, 2025

    • chimera

      Public
      Python
      •
      Other
      •2•14•9•1•Updated Jan 25, 2025Jan 25, 2025

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •6•46•0•0•Updated Jan 24, 2025Jan 24, 2025

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •52•220•8•17•Updated Jan 24, 2025Jan 24, 2025

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •717•17•0•5•Updated Jan 24, 2025Jan 24, 2025

    • chimera-sdk

      Public
      C
      •
      Apache License 2.0
      •4•3•7•3•Updated Jan 24, 2025Jan 24, 2025

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •58•59•15•7•Updated Jan 24, 2025Jan 24, 2025

    • pulp-sdk

      Public
      C
      •
      Apache License 2.0
      •75•102•14•6•Updated Jan 24, 2025Jan 24, 2025

    • artistic

      Public
      An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
      asicrenderinggdsii
      Python
      •
      Apache License 2.0
      •0•6•0•0•Updated Jan 24, 2025Jan 24, 2025

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •11•12•3•5•Updated Jan 24, 2025Jan 24, 2025

    • carfield

      Public
      A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
      casicfpgasimulationriscvsystemverilogsafety-criticalheterogeneous-computingmixed-criticality-systems
      Tcl
      •
      Other
      •14•80•17•5•Updated Jan 24, 2025Jan 24, 2025

    • redmule

      Public
      SystemVerilog
      •
      Other
      •12•41•1•3•Updated Jan 24, 2025Jan 24, 2025

    • ManyRVData

      Public
      0•0•0•0•Updated Jan 24, 2025Jan 24, 2025

    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      •67•1•0•2•Updated Jan 23, 2025Jan 23, 2025

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •18•86•1•2•Updated Jan 23, 2025Jan 23, 2025

    • pulpissimo

      Public
      This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
      SystemVerilog
      •
      Other
      •169•399•125•3•Updated Jan 23, 2025Jan 23, 2025

    • pulp_soc

      Public
      pulp_soc is the core building component of PULP based SoCs
      riscvsystemverilogpulp
      Python
      •
      Other
      •81•79•5•6•Updated Jan 23, 2025Jan 23, 2025

    • adv_dbg_if

      Public
      Advanced Debug Interface
      SystemVerilog
      •16•12•3•0•Updated Jan 23, 2025Jan 23, 2025

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •21•68•4•5•Updated Jan 23, 2025Jan 23, 2025

    • picobello

      Public
      SystemVerilog
      •
      Other
      •0•2•0•0•Updated Jan 22, 2025Jan 22, 2025

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •273•1.2k•44•9•Updated Jan 22, 2025Jan 22, 2025

    • tech_cells_generic

      Public
      Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
      SystemVerilog
      •
      Other
      •29•42•1•5•Updated Jan 21, 2025Jan 21, 2025

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •134•394•64•7•Updated Jan 20, 2025Jan 20, 2025

    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •10•22•4•4•Updated Jan 17, 2025Jan 17, 2025

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •118•12•0•4•Updated Jan 17, 2025Jan 17, 2025

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •150•556•31•8•Updated Jan 15, 2025Jan 15, 2025

    • occamy

      Public
      A high-efficiency system-on-chip for floating-point compute workloads.
      Python
      •
      Apache License 2.0
      •15•26•7•1•Updated Jan 13, 2025Jan 13, 2025

    • opensbi

      Public
      RISC-V Open Source Supervisor Binary Interface
      C
      •
      Other
      •531•0•0•2•Updated Jan 10, 2025Jan 10, 2025

    • CHERI-Litmus

      Public
      A tool to run litmus tests on bare-metal hardware
      C
      •
      Other
      •12•2•0•1•Updated Jan 9, 2025Jan 9, 2025