Add SHA_NI instruction check to the SIMD headers

This commit adds the function zfs_shani_available() to the libspl, os/freebsd and os/linux headers. Signed-off-by: Tino Reichardt <[email protected]>
openzfs · Aug 5, 2022 · 3886f99 · 3886f99
1 parent 634b6f6
commit 3886f99
Show file tree

Hide file tree

Showing 3 changed files with 41 additions and 1 deletion.
diff --git a/include/os/freebsd/spl/sys/simd_x86.h b/include/os/freebsd/spl/sys/simd_x86.h
@@ -173,6 +173,19 @@ zfs_avx2_available(void)
 	return (has_avx2 && __ymm_enabled());
 }
 
+/*
+ * Check if SHA_NI instruction set is available
+ */
+static inline boolean_t
+zfs_shani_available(void)
+{
+	boolean_t has_shani;
+
+	has_shani = !!(cpu_stdext_feature & CPUID_STDEXT_SHA);
+
+	return (has_shani && __ymm_enabled());
+}
+
 /*
  * AVX-512 family of instruction sets:
  *

diff --git a/include/os/linux/kernel/linux/simd_x86.h b/include/os/linux/kernel/linux/simd_x86.h
@@ -53,6 +53,8 @@
  *	zfs_bmi1_available()
  *	zfs_bmi2_available()
  *
+ *	zfs_shani_available()
+ *
  *	zfs_avx512f_available()
  *	zfs_avx512cd_available()
  *	zfs_avx512er_available()
@@ -586,6 +588,18 @@ zfs_movbe_available(void)
 #endif
 }
 
+/*
+ * Check if SHA_NI instruction set is available
+ */
+static inline boolean_t
+zfs_shani_available(void)
+{
+#if defined(X86_FEATURE_SHA_NI)
+	return (!!boot_cpu_has(X86_FEATURE_SHA_NI));
+#endif
+	return (B_FALSE);
+}
+
 /*
  * AVX-512 family of instruction sets:
  *

diff --git a/lib/libspl/include/sys/simd.h b/lib/libspl/include/sys/simd.h
@@ -78,7 +78,8 @@ typedef enum cpuid_inst_sets {
 	AVX512VL,
 	AES,
 	PCLMULQDQ,
-	MOVBE
+	MOVBE,
+	SHA_NI
 } cpuid_inst_sets_t;
 
 /*
@@ -103,6 +104,7 @@ typedef struct cpuid_feature_desc {
 #define	_AES_BIT		(1U << 25)
 #define	_PCLMULQDQ_BIT		(1U << 1)
 #define	_MOVBE_BIT		(1U << 22)
+#define	_SHA_NI_BIT		(1U << 29)
 
 /*
  * Descriptions of supported instruction sets
@@ -131,6 +133,7 @@ static const cpuid_feature_desc_t cpuid_features[] = {
 	[AES]		= {1U, 0U, _AES_BIT,		ECX	},
 	[PCLMULQDQ]	= {1U, 0U, _PCLMULQDQ_BIT,	ECX	},
 	[MOVBE]		= {1U, 0U, _MOVBE_BIT,		ECX	},
+	[SHA_NI]	= {7U, 0U, _SHA_NI_BIT,		EBX	},
 };
 
 /*
@@ -204,6 +207,7 @@ CPUID_FEATURE_CHECK(avx512vl, AVX512VL);
 CPUID_FEATURE_CHECK(aes, AES);
 CPUID_FEATURE_CHECK(pclmulqdq, PCLMULQDQ);
 CPUID_FEATURE_CHECK(movbe, MOVBE);
+CPUID_FEATURE_CHECK(shani, SHA_NI);
 
 /*
  * Detect register set support
@@ -345,6 +349,15 @@ zfs_movbe_available(void)
 	return (__cpuid_has_movbe());
 }
 
+/*
+ * Check if SHA_NI instruction is available
+ */
+static inline boolean_t
+zfs_shani_available(void)
+{
+	return (__cpuid_has_shani());
+}
+
 /*
  * AVX-512 family of instruction sets:
  *