feat: added page_read_chip and page_controller

[OsamaAlkhodairy]

spec: https://docs.google.com/document/d/1ajsBRZ6O5QRD5CgqlVfnc2c-tWh3gcUdbLH0KKE-3Js/edit

[jonathanpwang]

Mostly cosmetic changes requested. Can merge after addressing.

The main other change (for another PR) is that we need a slightly different version to handle indexed pages - these are where the key are several columns that are part of the cached trace, and we don't have an auto-generate index starting from 0.

I think there will be use cases for both, but not sure how to best refactor to make things as modular as possible. This is something to keep in mind when writing the read/write chip.

In other words, the current index column with the constraint that it auto-increments by 1, is not needed if the page itself has columns for keys. One option is to make that index column optional, and configurable in the chip constructor.

[jonathanpwang]

@OsamaAlkhodairy for future use, and to stabilize the Page interface, let's add the cached trace commitment of the page as a public value to the PageReadChip. However this requires being able to convert Com<SC> into a fixed length array. This may be a little annoying in that you'll need an additional trait bound on Com<SC>. Concretely for current testing utils, Com<SC> is this Hash type. DIGEST_WIDTH is the width here but we don't want to hard-code this since it will change if we change from poseidon2 to another hash. This means I think we need to have the commitment WIDTH in field elements as a const generic.

[jonathanpwang]

LGTM, change some debug prints to log