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VCS #677

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VCS #677

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3168859
updated install tool chain file to use verilator v5.016
Thomas-J-Kidd Jan 5, 2024
981c3cc
updated gitignore file
Thomas-J-Kidd Jan 5, 2024
ea8f424
merged script install file
Thomas-J-Kidd Jan 5, 2024
d09e0b1
Updating from main cvw repository
Thomas-J-Kidd Jan 10, 2024
1839580
Merging and hopefully tests can be made without errorsMerge branch 'm…
Thomas-J-Kidd Jan 11, 2024
14a0004
mergingMerge branch 'main' of github.com:Thomas-J-Kidd/cvw
Thomas-J-Kidd Jan 16, 2024
7871b1a
mergingMerge branch 'main' of github.com:Thomas-J-Kidd/cvw
Thomas-J-Kidd Jan 22, 2024
9165541
merging
Thomas-J-Kidd Jan 25, 2024
8d9f520
adding nightly tests
Thomas-J-Kidd Jan 31, 2024
7c3ea51
Merge branch 'main' of github.com:Thomas-J-Kidd/cvw
Thomas-J-Kidd Jan 31, 2024
942a280
reverted the verilator checkout to checkout master
Thomas-J-Kidd Jan 31, 2024
85f214a
Revert "reverted the verilator checkout to checkout master"
Thomas-J-Kidd Feb 1, 2024
590f53f
Revert "updated gitignore file"
Thomas-J-Kidd Feb 1, 2024
735785d
Merge branch 'openhwgroup:main' into main
Thomas-J-Kidd Feb 1, 2024
d2e606b
Revert "updated install tool chain file to use verilator v5.016"
Thomas-J-Kidd Feb 1, 2024
78db8c5
Revert "updated gitignore file"
Thomas-J-Kidd Feb 1, 2024
6398705
Merge branch 'openhwgroup:main' into main
Thomas-J-Kidd Feb 12, 2024
190ef91
Replacing nightly_build folder with nightly_build.py and bash wrapper…
Thomas-J-Kidd Feb 13, 2024
484613f
Merge branch 'openhwgroup:main' into main
Thomas-J-Kidd Feb 13, 2024
0cc0cde
initial seed of AES engine
stineje Feb 21, 2024
488583a
minor tweak
stineje Feb 21, 2024
93d9bb4
minor changes + date change on copyright
stineje Feb 21, 2024
2cf1d43
add aes instructions
stineje Feb 21, 2024
38348f9
Add SHA instructions
stineje Feb 21, 2024
32be225
add kmu instruction
stineje Feb 21, 2024
f700b7d
separate galois function SV per the style file
stineje Feb 21, 2024
3d65ea7
separate aes_shiftword per style file
stineje Feb 21, 2024
ac9068d
update aes_common with style on separate sv
stineje Feb 21, 2024
7097b17
update aes_instructions
stineje Feb 21, 2024
7cb170c
update on aes_instructions
stineje Feb 21, 2024
550f50d
Modify ALU to handle Zkne/K extension
stineje Feb 22, 2024
171da97
add config for K extensions (7 so far)
stineje Feb 22, 2024
c8468e9
slight tweak of names
stineje Feb 22, 2024
cdd2aa6
tweak of names
stineje Feb 22, 2024
4c84b9d
updated nightly build, but ran into buildroot errors
Thomas-J-Kidd Feb 23, 2024
e06bafe
Add alu + controller
stineje Feb 25, 2024
50cbe54
Add datapath.sv
stineje Feb 25, 2024
cd2a9b8
Add mux7 for K ext
stineje Feb 25, 2024
71cefdb
main cvw module
stineje Feb 25, 2024
ce975a6
Add ieu main module for k extension
stineje Feb 25, 2024
eb1780a
control for bitmanip
stineje Feb 25, 2024
0d4d996
add spike riscof items for K extension test
stineje Feb 25, 2024
01c45ab
Fixed K extension changes
KelvinTr Feb 28, 2024
88d93b3
Combined byteop and revop logic
KelvinTr Feb 29, 2024
e40ae12
Combined ZBC and ZBKC into one unit
KelvinTr Feb 29, 2024
9f53c54
Optimized Zbkx
KelvinTr Feb 29, 2024
c110d0b
Optimized Zbkx
KelvinTr Feb 29, 2024
c163069
Optimized mixcolumn
KelvinTr Mar 4, 2024
9ccc93f
over rides TIMEOUT on -nightly tag for regression since buildroot is …
Thomas-J-Kidd Mar 5, 2024
b2d0f71
Merge branch 'openhwgroup:main' into main
Thomas-J-Kidd Mar 5, 2024
e6ffde6
fix module name to lc
stineje Mar 5, 2024
0d7ea36
fix module name to lc in aes_instructions
stineje Mar 5, 2024
7bbc641
fix spacing in sha_instructions for style
stineje Mar 5, 2024
5e247b9
fix some spacing in aes_common
stineje Mar 5, 2024
5aab40a
Missed some style module declarations
stineje Mar 5, 2024
6894ee4
Separate gm2.sv to be separate module
stineje Mar 5, 2024
5b44594
style file slight mods for sha_instructions
stineje Mar 5, 2024
22947e5
udpated readme by adding how to add crontab section
Thomas-J-Kidd Mar 5, 2024
baa29ea
Merge branch 'openhwgroup:main' into main
Thomas-J-Kidd Mar 5, 2024
00b6139
Optimized Inverse Mixcolumn
KelvinTr Mar 5, 2024
b1830b1
Merge branch 'openhwgroup:main' into main
Thomas-J-Kidd Mar 6, 2024
2c6588d
Timinig optimization for radix 4 division, added missing derived config
davidharrishmc Mar 6, 2024
eb87a4a
UM comments in fdivsqrtotfc
davidharrishmc Mar 6, 2024
24dffa3
Yay. David and I got our first Quad load/store instructions working!
rosethompson Mar 7, 2024
1872966
Progress.
rosethompson Mar 7, 2024
a85ace8
Sold progress towards a decent q test.
rosethompson Mar 7, 2024
402d71e
Added basic Quad testing.
rosethompson Mar 7, 2024
7f28c9d
Merge pull request #656 from ross144/main
davidharrishmc Mar 7, 2024
e870e81
Finished Wally rvvi tracer.
rosethompson Mar 8, 2024
f815d56
Fix typo in Makefile.
Mar 8, 2024
c71cafb
Add linux/buildroot to .gitignore to ignore the intermediate built fo…
Mar 8, 2024
6bf2f16
Merge pull request #660 from Karl-Han/update_gitignore
rosethompson Mar 9, 2024
f7fa1cd
Merge pull request #657 from ross144/main
davidharrishmc Mar 9, 2024
8821386
update removal of underscores from aes_common
stineje Mar 9, 2024
08c7ddd
update removal of underscores from aes_instructions
stineje Mar 9, 2024
4addee0
updated nightly runs with try statement in email sending
Thomas-J-Kidd Mar 9, 2024
26f75b6
Merge branch 'main' of github.com:Thomas-J-Kidd/cvw
Thomas-J-Kidd Mar 9, 2024
0e3341c
added argstrings to make it a better CLI tool
Thomas-J-Kidd Mar 9, 2024
3b16238
update removal of underscores from sha_instructions
stineje Mar 10, 2024
55e019c
update removal of underscores from kmu
stineje Mar 10, 2024
bd5741b
fix space at beginning of file in bmu
stineje Mar 10, 2024
d3b1ce4
Merge branch 'openhwgroup:main' into main
Thomas-J-Kidd Mar 10, 2024
0caed8f
undo changing TIMEOUT duration for regression-wally
Thomas-J-Kidd Mar 10, 2024
c8df291
updated nightly runs with try statement in email sending
Thomas-J-Kidd Mar 9, 2024
ad12def
fix underscore in instantiation
stineje Mar 10, 2024
1aa1608
fix space in kmu
stineje Mar 10, 2024
7f65718
fixed documentation typo
Thomas-J-Kidd Mar 10, 2024
ac3aa82
fix underscore in bmu directory
stineje Mar 10, 2024
1573c89
Update bitmanipalu.sv for K extension
stineje Mar 10, 2024
54fec7c
fix bitmanipalu.sv typo on missing semicolon
stineje Mar 10, 2024
047291e
add header for bmuctrl.sv
stineje Mar 10, 2024
3cf6a19
Merge branch 'main' into main
rosethompson Mar 10, 2024
93d9af6
Merge pull request #640 from stineje/main
rosethompson Mar 10, 2024
93455e8
Added arch64i tests for fp configs
davidharrishmc Mar 11, 2024
39ca709
Merged AES changes
davidharrishmc Mar 11, 2024
34058dd
Crypto formatting cleanup
davidharrishmc Mar 11, 2024
e4724b8
Crypto formatting cleanup
davidharrishmc Mar 11, 2024
ea6846f
Crypto commenting cleanup
davidharrishmc Mar 11, 2024
955c131
Crypto rename inputs and outputs to a and y
davidharrishmc Mar 11, 2024
d0dd308
ZK simplification
davidharrishmc Mar 11, 2024
837abf1
ZK simplifcations
davidharrishmc Mar 11, 2024
2580d37
ZK cleanup, check no LLEN > XLEN without D$, add half and quad float …
davidharrishmc Mar 11, 2024
9a1fdba
Added more Zbkb tests shared with Zbb
davidharrishmc Mar 11, 2024
3d72cca
AES simplification
davidharrishmc Mar 11, 2024
f72e504
Defined rotate module and formatted AES modules more densely
davidharrishmc Mar 11, 2024
f950067
Shared middle and final round aes32 to cut size 50%
davidharrishmc Mar 11, 2024
b53e873
shared hardware for AES 64 decode
davidharrishmc Mar 11, 2024
d22306a
Shared haredware for aes64e
davidharrishmc Mar 11, 2024
7ee3145
Simplified muxing for AES64
davidharrishmc Mar 11, 2024
5257d3d
AES64 cleanup
davidharrishmc Mar 11, 2024
ef89679
Optimized out aes64im hardware; sharing with aes64d
davidharrishmc Mar 11, 2024
87ed778
Starting to merge decrypt and encrypt for AES64
davidharrishmc Mar 11, 2024
7d87c4f
AES64 simplification
davidharrishmc Mar 11, 2024
64d7f77
AES64 simplification
davidharrishmc Mar 11, 2024
b7f5ce6
AES64 simplification
davidharrishmc Mar 11, 2024
39c0d0c
AES64 simplification
davidharrishmc Mar 11, 2024
10d1ff6
Merged ZKNDEResult into a single BMU result mux input
davidharrishmc Mar 11, 2024
a714904
Simplifying AES32 logic
davidharrishmc Mar 11, 2024
8af25a4
AES32 sharing logic
davidharrishmc Mar 11, 2024
096f409
Final cleanup tonight
davidharrishmc Mar 11, 2024
019458a
Shared sbox between aes64ks1i and aes64e
davidharrishmc Mar 11, 2024
dbfe44a
Renamed aes and sha directories
davidharrishmc Mar 11, 2024
7132d30
Simplified ZKNH64
davidharrishmc Mar 11, 2024
ef2c003
Merge pull request #663 from davidharrishmc/dev
rosethompson Mar 11, 2024
55863bd
Update K extension in SHA to remove redundant logic and optimize hier…
stineje Mar 12, 2024
d11afcf
Merge pull request #666 from stineje/main
davidharrishmc Mar 12, 2024
41ab94c
fix elements forgot to delete from zknh32.sv
stineje Mar 12, 2024
4695418
Merge pull request #667 from stineje/main
davidharrishmc Mar 12, 2024
640dae6
System independent setup.sh file
rosethompson Mar 12, 2024
c027fd3
Added site-setup.csh for cshell systems.
rosethompson Mar 12, 2024
f642043
Fixed typos in site-setup.csh.
rosethompson Mar 12, 2024
700dfcc
Merge pull request #668 from ross144/site-setup
davidharrishmc Mar 12, 2024
a459f70
Merge pull request #669 from Karl-Han/fix_makefile_typo
rosethompson Mar 13, 2024
32763ab
Merge branch 'openhwgroup:main' into main
Thomas-J-Kidd Mar 13, 2024
e568f93
typo fixes
Thomas-J-Kidd Mar 13, 2024
b5419cc
Increase number of jobs in riscof to speedup building.
Mar 13, 2024
5e3ff3e
Merge pull request #671 from Karl-Han/increase_riscof_jobs
davidharrishmc Mar 13, 2024
90026a5
showing commands used for executing each specific test
Thomas-J-Kidd Mar 14, 2024
7ed2d0c
typo fix for displaying commands in email
Thomas-J-Kidd Mar 14, 2024
efc1d66
Merge pull request #673 from Thomas-J-Kidd/main
davidharrishmc Mar 14, 2024
cbd61d0
fix size of CVTLEN to support fcvtmod.w.d; add max macro to config-sh…
jordancarlin Mar 14, 2024
c3a0310
Merge pull request #674 from jordancarlin/main
davidharrishmc Mar 14, 2024
b476707
add derived configs directory to wally.do
jordancarlin Mar 14, 2024
36e45a0
Merge pull request #675 from jordancarlin/main
davidharrishmc Mar 14, 2024
4c30865
Update VCS Testbench run setup in Makefile
Divya2030 Mar 16, 2024
914a523
Merge remote-tracking branch 'origin/vcs' into vcs
Divya2030 Mar 16, 2024
5993de7
removing empty.sv file
Divya2030 Mar 23, 2024
f2cd1bf
run_vcs.sh script
Divya2030 Mar 23, 2024
c8a5c50
add run_xcellium
Divya2030 Mar 23, 2024
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update removal of underscores from aes_instructions
  • Loading branch information
stineje committed Mar 9, 2024
commit 08c7ddd61d6ebd7334801e781e1032efacf44175
22 changes: 11 additions & 11 deletions src/ieu/aes_instructions/aes32dsi.sv
Original file line number Diff line number Diff line change
@@ -28,32 +28,32 @@
module aes32dsi(input logic [1:0] bs,
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] Data_Out);
output logic [31:0] DataOut);

// Declare Intermediary logic
logic [4:0] shamt;
logic [31:0] Sbox_In_32;
logic [7:0] Sbox_In;
logic [7:0] Sbox_Out;
logic [31:0] SboxIn32;
logic [7:0] SboxIn;
logic [7:0] SboxOut;
logic [31:0] so;
logic [31:0] so_rotate;
logic [31:0] sorotate;

// shamt = bs * 8
assign shamt = {bs, 3'b0};

// Shift rs2 right by shamt and take the lower byte
assign Sbox_In_32 = (rs2 >> shamt);
assign Sbox_In = Sbox_In_32[7:0];
assign SboxIn32 = (rs2 >> shamt);
assign SboxIn = SboxIn32[7:0];

// Apply inverse sbox to si
aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out));
aesinvsbox inv_sbox(.in(SboxIn), .out(SboxOut));

// Pad output of inverse substitution box
assign so = {24'h0, Sbox_Out};
assign so = {24'h0, SboxOut};

// Rotate the substitution box output left by shamt (bs * 8)
assign so_rotate = (so << shamt) | (so >> (32 - shamt));
assign sorotate = (so << shamt) | (so >> (32 - shamt));

// Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));"
assign Data_Out = rs1 ^ so_rotate;
assign DataOut = rs1 ^ sorotate;
endmodule
24 changes: 12 additions & 12 deletions src/ieu/aes_instructions/aes32dsmi.sv
Original file line number Diff line number Diff line change
@@ -28,36 +28,36 @@
module aes32dsmi(input logic [1:0] bs,
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] Data_Out);
output logic [31:0] DataOut);

// Declare Intermediary logic
logic [4:0] shamt;
logic [31:0] Sbox_In_32;
logic [7:0] Sbox_In;
logic [7:0] Sbox_Out;
logic [31:0] SboxIn32;
logic [7:0] SboxIn;
logic [7:0] SboxOut;
logic [31:0] so;
logic [31:0] mixed;
logic [31:0] mixed_rotate;
logic [31:0] mixedrotate;

// shamt = bs * 8
assign shamt = {bs, 3'b0};

// Shift rs2 right by shamt and take the lower byte
assign Sbox_In_32 = (rs2 >> shamt);
assign Sbox_In = Sbox_In_32[7:0];
assign SboxIn32 = (rs2 >> shamt);
assign SboxIn = SboxIn32[7:0];

// Apply inverse sbox to si
aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out));
aesinvsbox inv_sbox(.in(SboxIn), .out(SboxOut));

// Pad output of inverse substitution box
assign so = {24'h0, Sbox_Out};
assign so = {24'h0, SboxOut};

// Run so through the mixword AES function
aes_inv_mixcolumns mix(.in(so), .out(mixed));
aesinvmixcolumns mix(.in(so), .out(mixed));

// Rotate the substitution box output left by shamt (bs * 8)
assign mixed_rotate = (mixed << shamt) | (mixed >> (32 - shamt));
assign mixedrotate = (mixed << shamt) | (mixed >> (32 - shamt));

// Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));"
assign Data_Out = rs1 ^ mixed_rotate;
assign DataOut = rs1 ^ mixedrotate;
endmodule
22 changes: 11 additions & 11 deletions src/ieu/aes_instructions/aes32esi.sv
Original file line number Diff line number Diff line change
@@ -28,34 +28,34 @@
module aes32esi(input logic [1:0] bs,
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] Data_Out);
output logic [31:0] DataOut);

// Declare Intermediary logic
logic [4:0] shamt;
logic [31:0] Sbox_In_32;
logic [7:0] Sbox_In;
logic [7:0] Sbox_Out;
logic [31:0] SboxIn32;
logic [7:0] SboxIn;
logic [7:0] SboxOut;
logic [31:0] so;
logic [31:0] so_rotate;
logic [31:0] sorotate;

// Shift bs by 3 to get shamt
assign shamt = {bs, 3'b0};

// Shift rs2 right by shamt to get sbox input
assign Sbox_In_32 = (rs2 >> shamt);
assign SboxIn32 = (rs2 >> shamt);

// Take the bottom byte as an input to the substitution box
assign Sbox_In = Sbox_In_32[7:0];
assign SboxIn = SboxIn32[7:0];

// Substitute
aes_sbox subbox(.in(Sbox_In), .out(Sbox_Out));
aessbox subbox(.in(SboxIn), .out(SboxOut));

// Pad sbox output
assign so = {24'h0, Sbox_Out};
assign so = {24'h0, SboxOut};

// Rotate so left by shamt
assign so_rotate = (so << shamt) | (so >> (32 - shamt));
assign sorotate = (so << shamt) | (so >> (32 - shamt));

// Set result X(rs1)[31..0] ^ rol32(so, unsigned(shamt));
assign Data_Out = rs1 ^ so_rotate;
assign DataOut = rs1 ^ sorotate;
endmodule
26 changes: 13 additions & 13 deletions src/ieu/aes_instructions/aes32esmi.sv
Original file line number Diff line number Diff line change
@@ -28,38 +28,38 @@
module aes32esmi(input logic [1:0] bs,
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] Data_Out);
output logic [31:0] DataOut);

// Declare Intermediary logic
logic [4:0] shamt;
logic [31:0] Sbox_In_32;
logic [7:0] Sbox_In;
logic [7:0] Sbox_Out;
logic [31:0] SboxIn32;
logic [7:0] SboxIn;
logic [7:0] SboxOut;
logic [31:0] so;
logic [31:0] mixed;
logic [31:0] mixed_rotate;
logic [31:0] mixedrotate;

// Shift bs by 3 to get shamt
assign shamt = {bs, 3'b0};

// Shift rs2 right by shamt to get sbox input
assign Sbox_In_32 = (rs2 >> shamt);
assign SboxIn32 = (rs2 >> shamt);

// Take the bottom byte as an input to the substitution box
assign Sbox_In = Sbox_In_32[7:0];
assign SboxIn = SboxIn32[7:0];

// Substitute
aes_sbox sbox(.in(Sbox_In), .out(Sbox_Out));
aessbox sbox(.in(SboxIn), .out(SboxOut));

// Pad sbox output
assign so = {24'h0, Sbox_Out};
assign so = {24'h0, SboxOut};

// Mix Word using aes_mixword component
aes_mixcolumns mwd(.in(so), .out(mixed));
// Mix Word using aesmixword component
aesmixcolumns mwd(.in(so), .out(mixed));

// Rotate so left by shamt
assign mixed_rotate = (mixed << shamt) | (mixed >> (32 - shamt));
assign mixedrotate = (mixed << shamt) | (mixed >> (32 - shamt));

// Set result X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt));
assign Data_Out = rs1 ^ mixed_rotate;
assign DataOut = rs1 ^ mixedrotate;
endmodule
16 changes: 8 additions & 8 deletions src/ieu/aes_instructions/aes64ds.sv
Original file line number Diff line number Diff line change
@@ -27,20 +27,20 @@

module aes64ds(input logic [63:0] rs1,
input logic [63:0] rs2,
output logic [63:0] Data_Out);
output logic [63:0] DataOut);

// Intermediary Logic
logic [127:0] ShiftRow_Out;
logic [31:0] Sbox_Out_0;
logic [31:0] Sbox_Out_1;
logic [127:0] ShiftRowOut;
logic [31:0] SboxOut0;
logic [31:0] SboxOut1;

// Apply inverse shiftrows to rs2 and rs1
aes_inv_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out));
aesinvshiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRowOut));

// Apply full word inverse substitution to lower 2 words of shiftrow out
aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0));
aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1));
aesinvsboxword inv_sbox_0(.in(ShiftRowOut[31:0]), .out(SboxOut0));
aesinvsboxword inv_sbox_1(.in(ShiftRowOut[63:32]), .out(SboxOut1));

// Concatenate the two substitution outputs to get result
assign Data_Out = {Sbox_Out_1, Sbox_Out_0};
assign DataOut = {SboxOut1, SboxOut0};
endmodule
24 changes: 12 additions & 12 deletions src/ieu/aes_instructions/aes64dsm.sv
Original file line number Diff line number Diff line change
@@ -27,26 +27,26 @@

module aes64dsm(input logic [63:0] rs1,
input logic [63:0] rs2,
output logic [63:0] Data_Out);
output logic [63:0] DataOut);

// Intermediary Logic
logic [127:0] ShiftRow_Out;
logic [31:0] Sbox_Out_0;
logic [31:0] Sbox_Out_1;
logic [31:0] Mixcol_Out_0;
logic [31:0] Mixcol_Out_1;
logic [127:0] ShiftRowOut;
logic [31:0] SboxOut0;
logic [31:0] SboxOut1;
logic [31:0] MixcolOut0;
logic [31:0] MixcolOut1;

// Apply inverse shiftrows to rs2 and rs1
aes_inv_shiftrow srow(.DataIn({rs2, rs1}), .DataOut(ShiftRow_Out));
aesinvshiftrow srow(.DataIn({rs2, rs1}), .DataOut(ShiftRowOut));

// Apply full word inverse substitution to lower 2 words of shiftrow out
aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0));
aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1));
aesinvsboxword invsbox0(.in(ShiftRowOut[31:0]), .out(SboxOut0));
aesinvsboxword invsbox1(.in(ShiftRowOut[63:32]), .out(SboxOut1));

// Apply inverse mixword to sbox outputs
aes_inv_mixcolumns inv_mw_0(.in(Sbox_Out_0), .out(Mixcol_Out_0));
aes_inv_mixcolumns inv_mw_1(.in(Sbox_Out_1), .out(Mixcol_Out_1));
aesinvmixcolumns invmw0(.in(SboxOut0), .out(MixcolOut0));
aesinvmixcolumns invmw1(.in(SboxOut1), .out(MixcolOut1));

// Concatenate mixed words for output
assign Data_Out = {Mixcol_Out_1, Mixcol_Out_0};
assign DataOut = {MixcolOut1, MixcolOut0};
endmodule
10 changes: 5 additions & 5 deletions src/ieu/aes_instructions/aes64es.sv
Original file line number Diff line number Diff line change
@@ -27,15 +27,15 @@

module aes64es(input logic [63:0] rs1,
input logic [63:0] rs2,
output logic [63:0] Data_Out);
output logic [63:0] DataOut);

// Intermediary Signals
logic [127:0] ShiftRow_Out;
logic [127:0] ShiftRowOut;

// AES shiftrow unit
aes_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out));
aesshiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRowOut));

// Apply substitution box to 2 lower words
aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Data_Out[31:0]));
aes_sbox_word sbox_1(.in(ShiftRow_Out[63:32]), .out(Data_Out[63:32]));
aessboxword sbox0(.in(ShiftRowOut[31:0]), .out(DataOut[31:0]));
aessboxword sbox1(.in(ShiftRowOut[63:32]), .out(DataOut[63:32]));
endmodule
16 changes: 8 additions & 8 deletions src/ieu/aes_instructions/aes64esm.sv
Original file line number Diff line number Diff line change
@@ -27,20 +27,20 @@

module aes64esm(input logic [63:0] rs1,
input logic [63:0] rs2,
output logic [63:0] Data_Out);
output logic [63:0] DataOut);

// Intermediary Signals
logic [127:0] ShiftRow_Out;
logic [63:0] Sbox_Out;
logic [127:0] ShiftRowOut;
logic [63:0] SboxOut;

// AES shiftrow unit
aes_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out));
aesshiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRowOut));

// Apply substitution box to 2 lower words
aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out[31:0]));
aes_sbox_word sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out[63:32]));
aessboxword sbox0(.in(ShiftRowOut[31:0]), .out(SboxOut[31:0]));
aessboxword sbox1(.in(ShiftRowOut[63:32]), .out(SboxOut[63:32]));

// Apply mix columns operations
aes_mixcolumns mw0(.in(Sbox_Out[31:0]), .out(Data_Out[31:0]));
aes_mixcolumns mw1(.in(Sbox_Out[63:32]), .out(Data_Out[63:32]));
aesmixcolumns mw0(.in(SboxOut[31:0]), .out(DataOut[31:0]));
aesmixcolumns mw1(.in(SboxOut[63:32]), .out(DataOut[63:32]));
endmodule
6 changes: 3 additions & 3 deletions src/ieu/aes_instructions/aes64im.sv
Original file line number Diff line number Diff line change
@@ -26,8 +26,8 @@
////////////////////////////////////////////////////////////////////////////////////////////////

module aes64im(input logic [63:0] rs1,
output logic [63:0] Data_Out);
output logic [63:0] DataOut);

aes_inv_mixcolumns inv_mw_0(.in(rs1[31:0]), .out(Data_Out[31:0]));
aes_inv_mixcolumns inv_mw_1(.in(rs1[63:32]), .out(Data_Out[63:32]));
aesinvmixcolumns inv_mw_0(.in(rs1[31:0]), .out(DataOut[31:0]));
aesinvmixcolumns inv_mw_1(.in(rs1[63:32]), .out(DataOut[63:32]));
endmodule
22 changes: 10 additions & 12 deletions src/ieu/aes_instructions/aes64ks1i.sv
Original file line number Diff line number Diff line change
@@ -30,33 +30,31 @@ module aes64ks1i(input logic [3:0] roundnum,
output logic [63:0] rd);

// Instantiate intermediary logic signals
logic [7:0] rcon_preshift;
logic [7:0] rconPreShift;
logic [31:0] rcon;
logic lastRoundFlag;
logic [31:0] rs1_rotate;
logic [31:0] rs1Rotate;
logic [31:0] tmp2;
logic [31:0] Sbox_Out;
logic [31:0] SboxOut;

// Get rcon value from table
rcon_lut_128 rc(.RD(roundnum), .rcon_out(rcon_preshift));
rconlut128 rc(.RD(roundnum), .rconOut(rconPreShift));

// Shift RCON value
assign rcon = {24'b0, rcon_preshift};
assign rcon = {24'b0, rconPreShift};

// Flag will be set if roundnum = 0xA = 0b1010
assign lastRoundFlag = roundnum[3] & ~roundnum[2] & roundnum[1] & ~roundnum[0];

// Get rotated value fo ruse in tmp2
assign rs1_rotate = {rs1[39:32], rs1[63:40]};
assign rs1Rotate = {rs1[39:32], rs1[63:40]};

// Assign tmp2 to a mux based on lastRoundFlag
assign tmp2 = lastRoundFlag ? rs1[63:32] : rs1_rotate;
assign tmp2 = lastRoundFlag ? rs1[63:32] : rs1Rotate;

// Substitute bytes of value obtained for tmp2 using Rijndael sbox
aes_sbox_word sbox(.in(tmp2),.out(Sbox_Out));
assign rd[31:0] = Sbox_Out ^ rcon;
assign rd[63:32] = Sbox_Out ^ rcon;


aessboxword sbox(.in(tmp2),.out(SboxOut));
assign rd[31:0] = SboxOut ^ rcon;
assign rd[63:32] = SboxOut ^ rcon;
endmodule

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