Refactored SPI peripheral #1052
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JacobPease
commented
Nov 2, 2024
JacobPease
commented
- Refactored SPI peripheral based on SPI controller module. Works in tests/custom/spitest.
- Fixed enabling of TransmitFIFOReadIncrement and ReceiveFIFOWriteIncrement
- Fixed issues relating to SCLKenable and TransmitStart. Works at multiple dividers now, instead of just SckDiv = 0.
- Added changed SPI controller module. New signal TransmitStartD that starts the FSM based on SCLKenable. TransmitStart is responsible for resetting SCLKenable and loading the Transmit Shift Register.
- Fixed FSM to continue transmitting after delay.
- Refactored SPI passes regression save for hardware interlock tests.
- Fixing latches.
- Fixed lint issues.
- Fixed ShiftEdge and SampleEdge to not always include PhaseOneOffset. Before, it worked in simulation, but not on the FPGA.
- Changed the condition for TransmitStart fsm to avoid edge condition.
- Cleaned up some code. Still more work to do there.
- Wrote a script that can take hexadecimal bytes from a file and write them to an output file and an sd card.
- Added usage and help functions to write-bytes.sh
- Reverted bootloader optimizations to second iteration. Working on last optimization.
…sts/custom/spitest.
…ple dividers now, instead of just SckDiv = 0.
…tarts the FSM based on SCLKenable. TransmitStart is responsible for resetting SCLKenable and loading the Transmit Shift Register.
…Before, it worked in simulation, but not on the FPGA.
…them to an output file and an sd card.
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