Fix reverted submodules

openhwgroup · Nov 2, 2024 · c64c6c4 · c64c6c4
1 parent 95fc056
commit c64c6c4
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Showing 3 changed files with 4 additions and 3 deletions.
diff --git a/.gitmodules b/.gitmodules
@@ -25,9 +25,10 @@
 	sparseCheckout = true
 	path = addins/verilog-ethernet
 	url = https://github.com/rosethompson/verilog-ethernet.git
-[submodule "cvw-arch-verif"]
+[submodule "addins/cvw-arch-verif"]
 	path = addins/cvw-arch-verif
 	url = https://github.com/openhwgroup/cvw-arch-verif
+	ignore = dirty
 [submodule "addins/riscvISACOV"]
 	path = addins/riscvISACOV
 	url = https://github.com/riscv-verification/riscvISACOV.git

diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif
diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test