Merge pull request #747 from davidharrishmc/dev

Zcb tests & other cleanup

.gitignore

@@ -203,3 +203,11 @@ benchmarks/coremark/coremark_results.csv
 fpga/zsbl/OBJ/*
 fpga/zsbl/bin/*
 sim/*.svg
+sim/vcs/csrc
+sim/vcs/profileReport*
+sim/vcs/program.out
+sim/vcs/sim_out*
+sim/vcs/simprofile_dir
+sim/vcs/ucli.key
+sim/vcs/verdi_config_file
+sim/*/testbench.vcd 

benchmarks/coremark/Makefile

@@ -12,6 +12,7 @@ sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h  \
 	$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
 ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32)
 ARCH := rv$(XLEN)im_zicsr_zba_zbb_zbs
+CONFIG := rv$(XLEN)gc
 #ARCH := rv$(XLEN)gc
 #ARCH := rv$(XLEN)imc_zicsr
 #ARCH := rv$(XLEN)im_zicsr
@@ -26,8 +27,9 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 
 all: $(work_dir)/coremark.bare.riscv.elf.memfile
 
-run:
-	time wsim rv$(XLEN)gc coremark 2>&1 | tee $(work_dir)/coremark.sim.log
+run: $(work_dir)/coremark.bare.riscv.elf.memfile
+#	time wsim rv$(XLEN)gc coremark --sim verilator 2>&1 | tee $(work_dir)/coremark.sim.log
+	time wsim ${CONFIG} coremark 2>&1 | tee $(work_dir)/coremark.sim.log
 
 $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
 	riscv64-unknown-elf-objdump -D $< > $<.elf.objdump

benchmarks/coremark/coremark_sweep.py

@@ -37,24 +37,26 @@
     "rv32i_zicsr",
     "rv32im_zicsr",
     "rv32imc_zicsr",
-    "rv32im_zicsr_zba_zbb_zbc",
+    "rv32im_zicsr_zba_zbb_zbs",
     "rv32gc",
-    "rv32gc_zba_zbb_zbc",
+    "rv32gc_zba_zbb_zbs",
     "rv64i_zicsr",
     "rv64im_zicsr",
     "rv64imc_zicsr",
-    "rv64im_zicsr_zba_zbb_zbc",
+    "rv64im_zicsr_zba_zbb_zbs",
     "rv64gc",
-    "rv64gc_zba_zbb_zbc"
+    "rv64gc_zba_zbb_zbs"
 ]
 str="32" 
+
 # Define regular expressions to match the desired fields
 mt_regex = r"Elapsed MTIME: (\d+).*?Elapsed MINSTRET: (\d+).*?COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+).*?CPI: \d+ / \d+ = (\d+\.\d+).*?Load Stalls (\d+).*?Store Stalls (\d+).*?D-Cache Accesses (\d+).*?D-Cache Misses (\d+).*?I-Cache Accesses (\d+).*?I-Cache Misses (\d+).*?Branches (\d+).*?Branches Miss Predictions (\d+).*?BTB Misses (\d+).*?Jump and JR (\d+).*?RAS Wrong (\d+).*?Returns (\d+).*?BP Class Wrong (\d+)"
 #cpi_regex = r"CPI: \d+ / \d+ = (\d+\.\d+)"
 #cmhz_regex = r"COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+)"
 # Open a CSV file to write the results
-with open('coremark_results.csv', mode='w', newline='') as csvfile:
-    fieldnames = ['Architecture', 'MTIME','MINSTRET','CM / MHz','CPI','Load Stalls','Store Stalls','D$ Accesses',
+resultfile = 'coremark_results.csv'
+with open(resultfile, mode='w', newline='') as csvfile:
+    fieldnames = ['Architecture', 'CM / MHz','CPI','MTIME','MINSTRET','Load Stalls','Store Stalls','D$ Accesses',
                     'D$ Misses','I$ Accesses','I$ Misses','Branches','Branch Mispredicts','BTB Misses',
                     'Jump/JR','RAS Wrong','Returns','BP Class Pred Wrong']
     writer = csv.DictWriter(csvfile, fieldnames=fieldnames)
@@ -101,7 +103,11 @@
         ret= mt_match.group(16)
         bpc= mt_match.group(17)
         #minstret = mt_instret_match.group(2)
-        writer.writerow({'Architecture': arch, 'MTIME': mtime,'MINSTRET':minstret,'CM / MHz':cmhz,'CPI':cpi,
+        writer.writerow({'Architecture': arch, 'CM / MHz':cmhz,'CPI':cpi, 'MTIME': mtime,'MINSTRET':minstret,
                             'Load Stalls':lstalls,
                             'Store Stalls':swtalls,'D$ Accesses':dacc,'D$ Misses':dmiss,'I$ Accesses':iacc,'I$ Misses':imiss,
                             'Branches':br,'Branch Mispredicts':brm,'BTB Misses':btb,'Jump/JR':jmp,'RAS Wrong':ras,'Returns':ret,'BP Class Pred Wrong':bpc})
+        csvfile.flush()
+    csvfile.close()
+
+

bin/lint-wally

@@ -26,7 +26,7 @@ fi
 
 for config in ${configs[@]}; do
 #    echo "$config linting..."
-    if !($verilator --no-timing --lint-only --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
+    if !($verilator --no-timing --lint-only --quiet --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
         if [ "$1" == "-nightly" ]; then
             echo -e "${RED}$config failed lint${NC}"
             fails=$((fails+1))

bin/regression-wally

@@ -30,30 +30,30 @@ tests = [
         ["rv32gc", ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", 
                     "arch32i", "arch32priv", "arch32c",  "arch32m", "arch32a", "arch32zifencei", "arch32zicond", 
                     "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", 
-                    "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", 
-                    "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], # "arch32zcb", "arch32zfad",
-        ["rv64i", ["arch64i"]]
+                    "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zcb",
+                    "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], #  "arch32zfad"  # fcvtmod.w.d not working because of Sail flag bug. Jordan has PR in to fix Sail
+         ["rv64i", ["arch64i"]]
         ]
 
-
-# Separate test for full buildroot run
+# Separate test for short buildroot run through OpenSBI UART output
 tests_buildrootshort = [
                     ["buildroot", ["buildroot"], [f"+INSTR_LIMIT=1400000"], # Instruction limit gets to first OpenSBI UART output  
                         "OpenSBI v", "buildroot_uart.out"]
     ]
 
+# Separate test for full buildroot run
 tests_buildrootboot = [
-                    ["buildroot", ["buildroot"], [f"+INSTR_LIMIT=600000000"], 
+                    ["buildroot", ["buildroot"], [f"+INSTR_LIMIT=600000000"], # boot entire buildroot Linux to login prompt
                         "WallyHostname login: ", "buildroot_uart.out"]
     ]
 
 
 # Separate out floating-point tests for RV64 to speed up coverage
 tests64gc_nofp = [
-        ["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m",
+        ["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m", "arch64zcb",
                     "arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv", 
                     "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
-                    "arch64zba",  "arch64zbb",  "arch64zbc", "arch64zbs"]] # add when working: "arch64zcb", "arch64zicboz"
+                    "arch64zba",  "arch64zbb",  "arch64zbc", "arch64zbs"]] # add when working:  "arch64zicboz"
     ]
 
 tests64gc_fp = [
@@ -237,6 +237,10 @@ def addTests(tests, sim):
 
 def search_log_for_text(text, grepfile):
     """Search through the given log file for text, returning True if it is found or False if it is not"""
+    grepwarn = "grep -H Warning: " + grepfile
+    os.system(grepwarn)
+    greperr = "grep -H Error: " + grepfile
+    os.system(greperr)
     grepcmd = "grep -a -e '%s' '%s' > /dev/null" % (text, grepfile)
 #    print("  search_log_for_text invoking %s" % grepcmd)
     return os.system(grepcmd) == 0
@@ -249,10 +253,11 @@ def run_test_case(config):
     # print("  run_test_case invoking %s" % cmd)
     os.system(cmd)
     if search_log_for_text(config.grepstr, grepfile):
-        print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name))
+#        print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name))
+        print(f"{bcolors.OKGREEN}%s: Success{bcolors.ENDC}" % (config.cmd))
         return 0
     else:
-        print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name))
+        print(f"{bcolors.FAIL}%s: Failures detected in output{bcolors.ENDC}" % (config.cmd))
         print("  Check %s" % grepfile)
         return 1
 
@@ -276,7 +281,8 @@ buildroot = '--buildroot' in sys.argv
 
 if (nightly):
     nightMode = "--nightly";
-    sims = ["questa", "verilator", "vcs"]
+    sims = [defaultsim] 
+#    sims = ["questa", "verilator", "vcs"] # *** uncomment to exercise all simulators
 else:
     nightMode = ""
     sims = [defaultsim]
@@ -309,8 +315,8 @@ else:
 
     # run derivative configurations in nightly regression
 if (nightly):
-    addTests(derivconfigtests, defaultsim)
     addTests(tests_buildrootboot, defaultsim)
+    addTests(derivconfigtests, defaultsim)
 else:
     addTests(tests_buildrootshort, defaultsim)
 
@@ -401,7 +407,7 @@ def main():
     elif '--nightly' in sys.argv:
         TIMEOUT_DUR = 60*1440 # 1 day
     elif '--testfloat' in sys.argv:
-        TIMEOUT_DUR = 60*60 # seconds
+        TIMEOUT_DUR = 5*60 # seconds
     else:
         TIMEOUT_DUR = 10*60 # seconds
 

bin/wally-tool-chain-install.sh

@@ -46,7 +46,7 @@ sudo mkdir -p $RISCV
 # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/)
 sudo apt update -y
 sudo apt upgrade -y
-sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev  gperf libtool patchutils bc mutt
+sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev  gperf libtool patchutils bc mutt ssmtp
 # Other python libraries used through the book.
 sudo pip3 install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown 
 

bin/wsim

@@ -70,6 +70,21 @@ if (args.sim == "questa"):
 elif (args.sim == "verilator"):
     # PWD=${WALLY}/sim CONFIG=rv64gc TESTSUITE=arch64i
     print(f"Running Verilator on {args.config} {args.testsuite}")
+    if (args.coverage):
+        print("Coverage option not available for Verilator")
+        exit(1)
+    if (args.gui):
+        print("GUI option not available for Verilator")
+        exit(1)
     os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite} EXTRA_ARGS='{args.args}'")
 elif (args.sim == "vcs"):
-    print("Running VCS on %s %s", args.config, args.testsuite)
+    print(f"Running VCS on " + args.config + " " + args.testsuite)
+    if (args.coverage):
+        print("Coverage option not available for VCS")
+        exit(1)
+    if (args.gui):
+        print("GUI option not available for VCS")
+        exit(1)
+    cmd = cd + "; ./run_vcs " + args.config + " " + "\""+args.testsuite+"\""
+    print(cmd)
+    os.system(cmd)

config/derivlist.txt

@@ -237,6 +237,9 @@ BURST_EN            1
 
 # Branch predictor simulations
 
+deriv nobpred_rv32gc rv32gc 
+BPRED_SUPPORTED     0
+
 deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc 
 BPRED_SIZE          32'd6
 

setup.sh

@@ -24,7 +24,7 @@ echo \$WALLY set to ${WALLY}
 export PATH=$WALLY/bin:$PATH    
 
 # Verilator needs a larger stack to simulate CORE-V Wally
-ulimit -s 100000
+ulimit -c 234613
 
 # load site licenses and tool locations
 if [ -f ${RISCV}/site-setup.sh ]; then

sim/vcs/run_vcs

@@ -0,0 +1,34 @@
+#!/bin/bash
+# VCS Compilation for WALLY
+# Divya Kohli, Rose Thompson, David Harris 2024
+# Note: VCS produces warning about unsupported Linux Version, but runs successfully
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+CFG=${WALLY}/config
+SRC=${WALLY}/src 
+TB=${WALLY}/testbench
+# Set CONFIG_VARIANT from the first script argument
+#CONFIG_VARIANT=${1:-rv64i}
+CONFIG_VARIANT=${1}
+# Set TESTSUITE from the second script argument
+TESTSUITE=$2
+
+
+INCLUDE_DIRS=$(find ${SRC} -type d | xargs -I {} echo -n "{} ")
+SOURCE_PATH="+incdir+${CFG}/${CONFIG_VARIANT} +incdir+${CFG}/deriv/${CONFIG_VARIANT} +incdir+${CFG}/shared +define+ +define+P.XLEN=64  +define+FPGA=0 +incdir+${TB} ${SRC}/cvw.sv +incdir+${SRC}" 
+
+SIMFILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/clockgater.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x64.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x32.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_512x64.sv")  ${TB}/testbench.sv $(find ${TB}/common -name "*.sv" ! -path "${TB}/common/wallyTracer.sv")" 
+OUTPUT="sim_out"
+
+clean() {
+    rm -rf obj_dir work transcript vsim.wlf $OUTPUT *.vcd csrc ucli.key vc_hdrs.h program.out
+    rm -rf simv* *.daidir dve *.vpd *.dump DVEfiles/ verdi* novas* *fsdb* *.vg *.rep *.db *.chk *.log *.out profileReport* simprofile_dir*
+}
+
+# Clean and run simulation with VCS
+clean
+#vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate  ${SOURCE_PATH} +define+TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
+# lint ignores Unused Inputs (UI), Unnamed Assertipons (SVA-UA), Dynamic Type Sensitivty [IDTS], Null Statement [NS], Unequal Length in Comparison Operation [ULCO]
+vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse  ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
+./$OUTPUT | tee program.out
+

sim/verilator/Makefile

@@ -1,3 +1,7 @@
+# Verilator Makefile for WALLY
+# Kunlin Han, Rose Thompson, David Harris 2024
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
 SHELL := /bin/bash
 .PHONY: profile run questa clean
 
@@ -6,7 +10,7 @@ OPT=
 PARAMS?=-DVERILATOR=1 --no-trace-top
 NONPROF?=--stats
 VERILATOR_DIR=${WALLY}/sim/verilator
-SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/config/${WALLYCONF} ${WALLY}/src/cvw.sv ${WALLY}/testbench/*.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
+SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/config/${WALLYCONF} ${WALLY}/config/deriv/${WALLYCONF} ${WALLY}/src/cvw.sv ${WALLY}/testbench/*.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
 EXTRA_ARGS=
 
 
@@ -37,22 +41,19 @@ profile: obj_dir_profiling/Vtestbench_$(WALLYCONF)
 
 run: wkdir/$(WALLYCONF)_$(TEST)/Vtestbench
 	mkdir -p $(VERILATOR_DIR)/logs
-	wkdir/$(WALLYCONF)_$(TEST)/Vtestbench +TEST=$(TEST) 2>&1 > $(VERILATOR_DIR)/logs/$(WALLYCONF)_$(TEST).log
-	echo "Please check $(VERILATOR_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files."
+	wkdir/$(WALLYCONF)_$(TEST)/Vtestbench +TEST=$(TEST)
 
-
-wkdir/$(WALLYCONF)_$(TEST)/Vtestbench: $(SOURCE)
+wkdir/$(WALLYCONF)_$(TEST)/Vtestbench: $(DEPENDENCIES)
 	verilator \
 	--Mdir wkdir/$(WALLYCONF)_$(TEST) -o Vtestbench \
 	--binary --trace \
 	$(OPT) $(PARAMS) $(NONPROF) \
 	$(EXTRA_ARGS) \
 	--timescale "1ns/1ns" --timing --top-module testbench  --relative-includes \
-	"-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" \
+	$(INCLUDE_PATH) \
 	${WALLY}/sim/verilator/wrapper.c \
-	${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
+	$(SOURCES)
 
-
 obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES)
 	mkdir -p obj_dir_profiling
 	verilator \
@@ -62,7 +63,7 @@ obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES)
 	$(EXTRA_ARGS) \
 	--timescale "1ns/1ns" --timing --top-module testbench  --relative-includes \
 	$(INCLUDE_PATH) \
-	wrapper.c \
+	${WALLY}/sim/verilator/wrapper.c \
 	$(SOURCES)
 
 questa:

sim/verilator/sim-wally-batch

@@ -0,0 +1 @@
+wsim -s verilator rv64gc arch64i

src/cache/cache.sv

@@ -215,9 +215,10 @@ module cache import cvw::*; #(parameter cvw_t P,
     assign FlushWayFlag = FlushWay[NUMWAYS-1];
   end // block: flushlogic
   else begin:flushlogic // I$ is never flushed because it is never dirty
-    assign FlushWay = 0;
-    assign FlushWayFlag = 0;
-    assign FlushAdrFlag = 0;
+    assign FlushWay = '0;
+    assign FlushWayFlag = 1'b0;
+    assign FlushAdrFlag = 1'b0;
+    assign FlushAdr = '0;
   end
 
   /////////////////////////////////////////////////////////////////////////////////////////////

src/cache/cacheLRU.sv

@@ -146,7 +146,7 @@ module cacheLRU
   // Move to = to keep Verilator happy and simulator running fast
   always_ff @(posedge clk) begin
     if (reset | (InvalidateCache & ~FlushStage)) 
-      for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = 0; // exclusion-tag: initialize
+      for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0; // exclusion-tag: initialize
     else if(CacheEn) begin
       // Because we are using blocking assignments, change to LRUMemory must occur after LRUMemory is used so we get the proper value
       if(LRUWriteEn & (PAdr == CacheSetTag)) CurrLRU = NextLRU;