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Fixed rmm rounding mode bug
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coreyqh committed Nov 3, 2024
1 parent 50f153a commit 0c6e9dc
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion src/fpu/fround.sv
Original file line number Diff line number Diff line change
Expand Up @@ -126,7 +126,7 @@ module fround import cvw::*; #(parameter cvw_t P) (
3'b001: RoundUp = 0; // RZ
3'b010: RoundUp = Xs & (Rp | Tp); // RN
3'b011: RoundUp = ~Xs & (Rp | Tp); // RP
3'b101: RoundUp = Rp; // RNTA
3'b100: RoundUp = Rp; // RNTA
default: RoundUp = 0; // should never happen
endcase

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