Added ZiCond Extension Support #1299
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I propose to enable Zicond for 64 bits configuration
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❌ failed run, report available here. |
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Hello @fatimasaleem Do not warry about the Thales CI status, the server is down. I will warm you when it will be fixed ! |
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Abdulwadoodd Once you confirm the status of Zicond arch-tests, I will mark this PR ready. |
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This PR is for implementation of Zicond ratified v1.0 (conditional integer operations) extension. As for the verification, I have just verified at the unit level. Currently, Zicond is in progress on the GCC (a patch is available). On LLVM, it is available in the current version(17).
The "Conditional" operations extension provides a simple solution that provides most of the benefits and flexibility one would desire to support conditional arithmetic and conditional-select/move operations while remaining true to the RISC-V design philosophy. The instructions follow the format for R-type instructions with three operands (i.e., two source operands and one destination operand). Using these instructions, branch-less sequences can be implemented (typically in two-instruction sequences) without the need for instruction fusion, special provisions during the decoding of architectural instructions, or other micro-architectural provisions.
Authored by: Asim Ahsan