Update rvfi_tracer and cva6.py (#2684)

* RVFI Tracer : Update tracer to support interrupts * Randomize sv_seed by default * Change pc64 to pc * Fixes * cva6.py : add the capability to create a log for sv_seed * Tracer : keep pc64 64 targets failed * Fix UVM seed for performance tests --------- Co-authored-by: André Sintzoff <[email protected]>
openhwgroup · Jan 31, 2025 · 70972da · 70972da
1 parent 10fced1
commit 70972da
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Showing 7 changed files with 45 additions and 16 deletions.
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -171,6 +171,7 @@ smoke-gen:
   script:
     - bash verif/regress/smoke-gen_tests.sh
     - cp verif/sim/seedlist.yaml artifacts/logs/
+    - cp verif/sim/uvm_seed.log artifacts/logs/
     - !reference [.simu_after_script]
 
 smoke-bench:
@@ -452,6 +453,7 @@ generated_tests:
     - source verif/regress/dv-generated-tests.sh
     - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
     - mv verif/sim/seedlist.yaml artifacts/coverage
+    - mv verif/sim/uvm_seed.log artifacts/coverage
     - python3 .gitlab-ci/scripts/report_pass.py
 
 .generated_xif_tests:
@@ -472,6 +474,7 @@ generated_tests:
     - source verif/regress/dv-generated-xif-tests.sh
     - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
     - mv verif/sim/seedlist.yaml artifacts/coverage
+    - mv verif/sim/uvm_seed.log artifacts/coverage
     - python3 .gitlab-ci/scripts/report_pass.py
 
 directed_isacov-tests:
@@ -491,6 +494,7 @@ directed_isacov-tests:
     - mkdir -p artifacts/coverage
     - source verif/regress/dv-generated-tests.sh
     - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
+    - mv verif/sim/uvm_seed.log artifacts/coverage
     - python3 .gitlab-ci/scripts/report_pass.py
 
 csr_embedded_tests:
@@ -507,6 +511,7 @@ csr_embedded_tests:
     - mkdir -p artifacts/coverage
     - source verif/regress/dv-csr-embedded-tests.sh
     - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
+    - mv verif/sim/uvm_seed.log artifacts/coverage
     - python3 .gitlab-ci/scripts/report_tandem.py verif/sim/out*/"$DV_SIMULATORS"_sim
 
 .backend_test:
@@ -605,6 +610,7 @@ code_coverage-report:
     - mkdir -p verif/sim/vcs_results/default/vcs.d
     - mv artifacts/coverage/simv.vdb verif/sim/vcs_results/default/vcs.d/
     - mv artifacts/coverage/seedlist.yaml verif/sim/seedlist.yaml
+    - mv artifacts/coverage/uvm_seed.log verif/sim/uvm_seed.log
     - make -C verif/sim generate_cov_dash
     - mv verif/sim/urgReport artifacts/cov_reports/
     - python3 .gitlab-ci/scripts/report_coverage.py artifacts/cov_reports/urgReport/hierarchy.txt artifacts/cov_reports/urgReport/"feature.CVA6 Verification Master Plan1.7.-1268999905.txt"

diff --git a/corev_apu/tb/rvfi_tracer.sv b/corev_apu/tb/rvfi_tracer.sv
@@ -78,8 +78,14 @@ module rvfi_tracer #(
       // print the instruction information if the instruction is valid or a trap is taken
       if (rvfi_i[i].valid) begin
         // Instruction information
-        $fwrite(f, "core   0: 0x%h (0x%h) DASM(%h)\n",
-          pc64, rvfi_i[i].insn, rvfi_i[i].insn);
+        if (rvfi_i[i].intr[2]) begin
+           $fwrite(f, "core   INTERRUPT 0: 0x%h (0x%h) DASM(%h)\n",
+             pc64, rvfi_i[i].insn, rvfi_i[i].insn);
+        end
+        else begin
+           $fwrite(f, "core   0: 0x%h (0x%h) DASM(%h)\n",
+             pc64, rvfi_i[i].insn, rvfi_i[i].insn);
+        end
         // Destination register information
         if (rvfi_i[i].insn[1:0] != 2'b11) begin
           $fwrite(f, "%h 0x%h (0x%h)",
@@ -129,8 +135,13 @@ module rvfi_tracer #(
             32'h5: cause = "LD_ACCESS_FAULT";
             32'h6: cause = "ST_ADDR_MISALIGNED";
             32'h7: cause = "ST_ACCESS_FAULT";
+            32'hb: cause = "ENV_CALL_MMODE";
           endcase;
-          $fwrite(f, "%s exception @ 0x%h\n", cause, pc64);
+          if (rvfi_i[i].insn[1:0] != 2'b11) begin
+            $fwrite(f, "%s exception @ 0x%h (0x%h)\n", cause, pc64, rvfi_i[i].insn[15:0]);
+          end else begin
+            $fwrite(f, "%s exception @ 0x%h (0x%h)\n", cause, pc64, rvfi_i[i].insn);
+          end
         end
       end
     end

diff --git a/verif/regress/benchmark.sh b/verif/regress/benchmark.sh
@@ -55,18 +55,18 @@ GCC_CFLAGS=(
 
 GCC_OPTS="${GCC_COMMON_SRC[*]} ${GCC_CFLAGS[*]}"
 
-python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/dhrystone/dhrystone_main.c --gcc_opts "$BDIR/dhrystone/dhrystone.c $GCC_OPTS -I$BDIR/dhrystone/"
-python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/median/median_main.c       --gcc_opts "$BDIR/median/median.c       $GCC_OPTS -I$BDIR/median/"
-python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/mm/mm.c                    --gcc_opts "$BDIR/mm/mm_main.c          $GCC_OPTS -I$BDIR/mm/"
-python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/mt-matmul/mt-matmul.c      --gcc_opts "$BDIR/mt-matmul/matmul.c    $GCC_OPTS -I$BDIR/mt-matmul/"
-python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/mt-vvadd/mt-vvadd.c        --gcc_opts "$BDIR/mt-vvadd/vvadd.c      $GCC_OPTS -I$BDIR/mt-vvadd/"
-python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/multiply/multiply_main.c   --gcc_opts "$BDIR/multiply/multiply.c   $GCC_OPTS -I$BDIR/multiply/"
-python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/pmp/pmp.c                  --gcc_opts "                            $GCC_OPTS -I$BDIR/pmp/"
-python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/qsort/qsort_main.c         --gcc_opts "                            $GCC_OPTS -I$BDIR/qsort/"
-python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/rsort/rsort.c              --gcc_opts "                            $GCC_OPTS -I$BDIR/rsort/"
-python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/spmv/spmv_main.c           --gcc_opts "                            $GCC_OPTS -I$BDIR/spmv/"
-python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/towers/towers_main.c       --gcc_opts "                            $GCC_OPTS -I$BDIR/towers/"
-python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/vvadd/vvadd_main.c         --gcc_opts "                            $GCC_OPTS -I$BDIR/vvadd/"
+python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/dhrystone/dhrystone_main.c --sv_seed 1 --gcc_opts "$BDIR/dhrystone/dhrystone.c $GCC_OPTS -I$BDIR/dhrystone/"
+python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/median/median_main.c       --sv_seed 1 --gcc_opts "$BDIR/median/median.c       $GCC_OPTS -I$BDIR/median/"
+python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/mm/mm.c                    --sv_seed 1 --gcc_opts "$BDIR/mm/mm_main.c          $GCC_OPTS -I$BDIR/mm/"
+python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/mt-matmul/mt-matmul.c      --sv_seed 1 --gcc_opts "$BDIR/mt-matmul/matmul.c    $GCC_OPTS -I$BDIR/mt-matmul/"
+python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/mt-vvadd/mt-vvadd.c        --sv_seed 1 --gcc_opts "$BDIR/mt-vvadd/vvadd.c      $GCC_OPTS -I$BDIR/mt-vvadd/"
+python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/multiply/multiply_main.c   --sv_seed 1 --gcc_opts "$BDIR/multiply/multiply.c   $GCC_OPTS -I$BDIR/multiply/"
+python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/pmp/pmp.c                  --sv_seed 1 --gcc_opts "                            $GCC_OPTS -I$BDIR/pmp/"
+python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/qsort/qsort_main.c         --sv_seed 1 --gcc_opts "                            $GCC_OPTS -I$BDIR/qsort/"
+python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/rsort/rsort.c              --sv_seed 1 --gcc_opts "                            $GCC_OPTS -I$BDIR/rsort/"
+python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/spmv/spmv_main.c           --sv_seed 1 --gcc_opts "                            $GCC_OPTS -I$BDIR/spmv/"
+python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/towers/towers_main.c       --sv_seed 1 --gcc_opts "                            $GCC_OPTS -I$BDIR/towers/"
+python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/vvadd/vvadd_main.c         --sv_seed 1 --gcc_opts "                            $GCC_OPTS -I$BDIR/vvadd/"
 
 make clean
 make -C verif/sim clean_all

diff --git a/verif/regress/coremark.sh b/verif/regress/coremark.sh
@@ -92,6 +92,7 @@ python3 cva6.py \
         --iss="$DV_SIMULATORS" \
         --iss_yaml=cva6.yaml \
         --c_tests "$src0" \
+        --sv_seed 1 \
         --gcc_opts "${srcA[*]} ${cflags[*]}" \
         --iss_timeout=2000 \
         $DV_OPTS
diff --git a/verif/regress/dhrystone.sh b/verif/regress/dhrystone.sh
@@ -69,5 +69,6 @@ python3 cva6.py \
         --iss="$DV_SIMULATORS" \
         --iss_yaml=cva6.yaml \
         --c_tests "$src0" \
+        --sv_seed 1 \
         --gcc_opts "${srcA[*]} ${cflags[*]}" \
         $DV_OPTS
diff --git a/verif/regress/dhrystone_smoke.sh b/verif/regress/dhrystone_smoke.sh
@@ -62,4 +62,5 @@ python3 cva6.py \
         --iss="$DV_SIMULATORS" \
         --iss_yaml=cva6.yaml \
         --c_tests "$src0" \
+        --sv_seed 1 \
         --gcc_opts "${srcA[*]} ${cflags[*]}"
diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py
@@ -431,6 +431,13 @@ def analyze_tandem_report(yaml_path):
   except KeyError:
     logging.info("Incomplete TANDEM YAML report")
 
+def log_uvm_seed(sv_seed , filename="uvm_seed.log"):
+  try:
+      with open(filename, 'a') as file:
+          timestamp = datetime.datetime.now().strftime('%Y-%m-%d  %H:%M:%S')
+          file.write(f"{timestamp} - UVM Seed: {sv_seed}\n")
+  except IOError as error:
+      print(f"Failed to log UVM seed: {error}")
 
 def generate_yaml_report(yaml_path, target, isa, test, testlist, iss, initial_creation , iteration = None):
   if not initial_creation:
@@ -775,7 +782,7 @@ def parse_args(cwd):
                       help="switch AXI agent mode: yes for Active, no for Passive")
   parser.add_argument("--gen_sv_seed", type=int, default=0,
                       help="Run test N times with random seed")
-  parser.add_argument("--sv_seed", type=str, default="1",
+  parser.add_argument("--sv_seed", type=str, default=str(random.getrandbits(31)),
                       help="Run test with a specific seed")
   parser.add_argument("--isa_extension", type=str, default="",
                       help="Choose additional z, s, x extensions")
@@ -1105,6 +1112,8 @@ def main():
     else:
       logging.error('gen_sv_seed can not take a negative value')
 
+    log_uvm_seed(args.sv_seed)
+
     issrun_opts = "\""+args.issrun_opts+"\""
 
     global isspostrun_opts