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Updated RISC-V Debug specification to version 1.0-STABLE, fb702526127… #834

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merged 2 commits into from
Apr 19, 2023

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Silabs-ArjanB
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…d0c8a4b343fc017e2c93137177df0, April 14 2023

  • Removed tcontrol CSR.
  • Removed tdata3 CSR.
  • Updated mcontrol6 bitfields according to Sdtrig version 1.
  • Updated tinfo CSR according to Sdtrig version 1.

…d0c8a4b343fc017e2c93137177df0, April 14 2023

Signed-off-by: Arjan Bink <[email protected]>
Signed-off-by: Arjan Bink <[email protected]>
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Perhaps no change is needed, but I wanted to raise the discussion on the writability of the hit0 and hit1 bits.

@silabs-oysteink silabs-oysteink merged commit f17028f into openhwgroup:master Apr 19, 2023
@Silabs-ArjanB Silabs-ArjanB added the Component:Doc For issues in the Documentation (e.g. for User Manual, README.md files) label Apr 19, 2023
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