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Renamed CLIC related parameters (removed SM prefix) #792

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Feb 22, 2023
Merged

Renamed CLIC related parameters (removed SM prefix) #792

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6 changes: 3 additions & 3 deletions bhv/cv32e40x_rvfi.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -22,9 +22,9 @@ module cv32e40x_rvfi
import cv32e40x_pkg::*;
import cv32e40x_rvfi_pkg::*;
#(
parameter bit SMCLIC = 0,
parameter int DEBUG = 1,
parameter a_ext_e A_EXT = A_NONE
parameter bit CLIC = 0,
parameter int DEBUG = 1,
parameter a_ext_e A_EXT = A_NONE
)
(
input logic clk_i,
Expand Down
32 changes: 16 additions & 16 deletions bhv/cv32e40x_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -64,9 +64,9 @@ module cv32e40x_wrapper
parameter logic [31:0] X_MISA = 32'h00000000,
parameter logic [1:0] X_ECS_XS = 2'b00,
parameter int NUM_MHPMCOUNTERS = 1,
parameter bit SMCLIC = 0,
parameter int SMCLIC_ID_WIDTH = 5,
parameter int SMCLIC_INTTHRESHBITS = 8,
parameter bit CLIC = 0,
parameter int CLIC_ID_WIDTH = 5,
parameter int CLIC_INTTHRESHBITS = 8,
parameter int DBG_NUM_TRIGGERS = 1,
parameter int PMA_NUM_REGIONS = 0,
parameter pma_cfg_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:PMA_R_DEFAULT},
Expand Down Expand Up @@ -142,7 +142,7 @@ module cv32e40x_wrapper

// CLIC Interface
input logic clic_irq_i,
input logic [SMCLIC_ID_WIDTH-1:0] clic_irq_id_i,
input logic [CLIC_ID_WIDTH-1:0] clic_irq_id_i,
input logic [ 7:0] clic_irq_level_i,
input logic [ 1:0] clic_irq_priv_i,
input logic clic_irq_shv_i,
Expand Down Expand Up @@ -228,7 +228,7 @@ module cv32e40x_wrapper
cv32e40x_controller_fsm_sva
#(.X_EXT(X_EXT),
.DEBUG(DEBUG),
.SMCLIC(SMCLIC))
.CLIC(CLIC))
controller_fsm_sva (
.lsu_outstanding_cnt (core_i.load_store_unit_i.cnt_q),
.rf_we_wb_i (core_i.wb_stage_i.rf_we_wb_o ),
Expand All @@ -251,7 +251,7 @@ module cv32e40x_wrapper
bind cv32e40x_cs_registers:
core_i.cs_registers_i
cv32e40x_cs_registers_sva
#(.SMCLIC(SMCLIC),
#(.CLIC (CLIC),
.DEBUG (DEBUG))
cs_registers_sva (.wb_valid_i (core_i.wb_valid ),
.ctrl_fsm_cs (core_i.controller_i.controller_fsm_i.ctrl_fsm_cs),
Expand Down Expand Up @@ -298,7 +298,7 @@ module cv32e40x_wrapper
bind cv32e40x_prefetch_unit:
core_i.if_stage_i.prefetch_unit_i
cv32e40x_prefetch_unit_sva
#(.SMCLIC(SMCLIC))
#(.CLIC(CLIC))
prefetch_unit_sva (
.ctrl_fsm_cs (core_i.controller_i.controller_fsm_i.ctrl_fsm_cs),
.debug_req_i (core_i.debug_req_i),
Expand All @@ -319,16 +319,16 @@ module cv32e40x_wrapper
bind cv32e40x_prefetcher:
core_i.if_stage_i.prefetch_unit_i.prefetcher_i
cv32e40x_prefetcher_sva
#(.SMCLIC(SMCLIC))
#(.CLIC(CLIC))
prefetcher_sva ( .prefetch_is_clic_ptr (core_i.if_stage_i.prefetch_unit_i.prefetch_is_clic_ptr_o),
.*);

bind cv32e40x_core:
core_i cv32e40x_core_sva
#(.A_EXT(A_EXT),
.DEBUG (DEBUG),
.DEBUG(DEBUG),
.PMA_NUM_REGIONS(PMA_NUM_REGIONS),
.SMCLIC(SMCLIC))
.CLIC(CLIC))
core_sva (// probed cs_registers signals
.cs_registers_mie_q (core_i.cs_registers_i.mie_q),
.cs_registers_mepc_n (core_i.cs_registers_i.mepc_n),
Expand Down Expand Up @@ -366,7 +366,7 @@ module cv32e40x_wrapper
.lsu_exokay_wb (core_i.data_exokay_i), // todo: Could poke into LSU, but this signal is fed directly through the LSU
.*);
generate
if (SMCLIC) begin : clic_asserts
if (CLIC) begin : clic_asserts
bind cv32e40x_clic_int_controller:
core_i.gen_clic_interrupt.clic_int_controller_i
cv32e40x_clic_int_controller_sva
Expand Down Expand Up @@ -473,7 +473,7 @@ endgenerate
bind cv32e40x_rvfi:
rvfi_i
cv32e40x_rvfi_sva
#(.SMCLIC(SMCLIC),
#(.CLIC (CLIC),
.DEBUG (DEBUG),
.A_EXT (A_EXT))
rvfi_sva(.irq_ack(core_i.irq_ack),
Expand Down Expand Up @@ -503,7 +503,7 @@ endgenerate
);

cv32e40x_rvfi
#(.SMCLIC(SMCLIC),
#(.CLIC (CLIC),
.DEBUG (DEBUG),
.A_EXT (A_EXT))
rvfi_i
Expand Down Expand Up @@ -785,9 +785,9 @@ endgenerate
.X_MISA ( X_MISA ),
.X_ECS_XS ( X_ECS_XS ),
.NUM_MHPMCOUNTERS ( NUM_MHPMCOUNTERS ),
.SMCLIC ( SMCLIC ),
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
.SMCLIC_INTTHRESHBITS ( SMCLIC_INTTHRESHBITS ),
.CLIC ( CLIC ),
.CLIC_ID_WIDTH ( CLIC_ID_WIDTH ),
.CLIC_INTTHRESHBITS ( CLIC_INTTHRESHBITS ),
.DEBUG ( DEBUG ),
.DM_REGION_START ( DM_REGION_START ),
.DM_REGION_END ( DM_REGION_END ),
Expand Down
10 changes: 5 additions & 5 deletions rtl/cv32e40x_clic_int_controller.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -28,15 +28,15 @@

module cv32e40x_clic_int_controller import cv32e40x_pkg::*;
#(
parameter int SMCLIC_ID_WIDTH = 5
parameter int CLIC_ID_WIDTH = 5
)
(
input logic clk,
input logic rst_n,

// CLIC interface
input logic clic_irq_i, // CLIC interrupt pending
input logic [SMCLIC_ID_WIDTH-1:0] clic_irq_id_i, // ID of pending interrupt
input logic [CLIC_ID_WIDTH-1:0] clic_irq_id_i, // ID of pending interrupt
input logic [7:0] clic_irq_level_i, // Level of pending interrupt
input logic [1:0] clic_irq_priv_i, // Privilege level of pending interrupt (always machine mode) (not used)
input logic clic_irq_shv_i, // Is pending interrupt vectored?
Expand All @@ -58,7 +58,7 @@ module cv32e40x_clic_int_controller import cv32e40x_pkg::*;

// To cs_registers
output logic mnxti_irq_pending_o, // An interrupt is available to the mnxti CSR read
output logic [SMCLIC_ID_WIDTH-1:0] mnxti_irq_id_o, // The id of the availble mnxti interrupt
output logic [CLIC_ID_WIDTH-1:0] mnxti_irq_id_o, // The id of the availble mnxti interrupt
output logic [7:0] mnxti_irq_level_o // Level of the available interrupt
);

Expand All @@ -67,7 +67,7 @@ module cv32e40x_clic_int_controller import cv32e40x_pkg::*;

// Flops for breaking timing path to instruction interface
logic clic_irq_q;
logic [SMCLIC_ID_WIDTH-1:0] clic_irq_id_q;
logic [CLIC_ID_WIDTH-1:0] clic_irq_id_q;
logic [7:0] clic_irq_level_q;
logic clic_irq_shv_q;

Expand Down Expand Up @@ -159,7 +159,7 @@ module cv32e40x_clic_int_controller import cv32e40x_pkg::*;

// If mnxti_irq_pending is true, the currently flopped ID and level will be sent to cs_registers
// for use in the function pointer and CSR side effects.
// Using native SMCLIC_ID_WIDTH for cleaner pointer concatenation in cs_registers.
// Using native CLIC_ID_WIDTH for cleaner pointer concatenation in cs_registers.

assign mnxti_irq_id_o = clic_irq_id_q;
assign mnxti_irq_level_o = clic_irq_level_q;
Expand Down
8 changes: 4 additions & 4 deletions rtl/cv32e40x_controller.sv
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Expand Up @@ -34,8 +34,8 @@ module cv32e40x_controller import cv32e40x_pkg::*;
parameter bit X_EXT = 0,
parameter a_ext_e A_EXT = A_NONE,
parameter int unsigned REGFILE_NUM_READ_PORTS = 2,
parameter bit SMCLIC = 0,
parameter int SMCLIC_ID_WIDTH = 5,
parameter bit CLIC = 0,
parameter int CLIC_ID_WIDTH = 5,
parameter int DEBUG = 1
)
(
Expand Down Expand Up @@ -147,8 +147,8 @@ module cv32e40x_controller import cv32e40x_pkg::*;
cv32e40x_controller_fsm
#(
.X_EXT ( X_EXT ),
.SMCLIC ( SMCLIC ),
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
.CLIC ( CLIC ),
.CLIC_ID_WIDTH ( CLIC_ID_WIDTH ),
.DEBUG ( DEBUG )
)
controller_fsm_i
Expand Down
12 changes: 6 additions & 6 deletions rtl/cv32e40x_controller_fsm.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -31,10 +31,10 @@

module cv32e40x_controller_fsm import cv32e40x_pkg::*;
#(
parameter bit X_EXT = 0,
parameter int DEBUG = 1,
parameter bit SMCLIC = 0,
parameter int SMCLIC_ID_WIDTH = 5
parameter bit X_EXT = 0,
parameter int DEBUG = 1,
parameter bit CLIC = 0,
parameter int CLIC_ID_WIDTH = 5
)
(
// Clocks and reset
Expand Down Expand Up @@ -461,7 +461,7 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*;
// Detect if there is a live CLIC pointer in the pipeline
// This should block debug and interrupts
generate
if (SMCLIC) begin : gen_clic_pointer_flag
if (CLIC) begin : gen_clic_pointer_flag
// A CLIC pointer may be in the pipeline from the moment we start fetching (clic_ptr_in_progress_id == 1)
// or while a pointer is in the EX or WB stages.
assign clic_ptr_in_pipeline = (id_ex_pipe_i.instr_valid && id_ex_pipe_i.instr_meta.clic_ptr) ||
Expand Down Expand Up @@ -776,7 +776,7 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*;
ctrl_fsm_o.csr_cause.minhv = mcause_i.minhv;


if (SMCLIC) begin
if (CLIC) begin
ctrl_fsm_o.csr_cause.exception_code = {1'b0, irq_id_ctrl_i};
ctrl_fsm_o.irq_level = irq_clic_level_i;
ctrl_fsm_o.irq_priv = irq_clic_priv_i;
Expand Down
40 changes: 20 additions & 20 deletions rtl/cv32e40x_core.sv
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Expand Up @@ -42,9 +42,9 @@ module cv32e40x_core import cv32e40x_pkg::*;
parameter int DBG_NUM_TRIGGERS = 1,
parameter int PMA_NUM_REGIONS = 0,
parameter pma_cfg_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:PMA_R_DEFAULT},
parameter bit SMCLIC = 0,
parameter int SMCLIC_ID_WIDTH = 5,
parameter int SMCLIC_INTTHRESHBITS = 8,
parameter bit CLIC = 0,
parameter int CLIC_ID_WIDTH = 5,
parameter int CLIC_INTTHRESHBITS = 8,
parameter bit X_EXT = 0,
parameter int X_NUM_RS = 2,
parameter int X_ID_WIDTH = 4,
Expand Down Expand Up @@ -117,9 +117,9 @@ module cv32e40x_core import cv32e40x_pkg::*;
input logic wu_wfe_i, // Wait-for-event wakeup
input logic wu_wrs_i, // Wait-for-reservation-set wakeup

// Smclic interrupt architecture
// CLIC interrupt architecture
input logic clic_irq_i,
input logic [SMCLIC_ID_WIDTH-1:0] clic_irq_id_i,
input logic [CLIC_ID_WIDTH-1:0] clic_irq_id_i,
input logic [ 7:0] clic_irq_level_i,
input logic [ 1:0] clic_irq_priv_i,
input logic clic_irq_shv_i,
Expand Down Expand Up @@ -151,7 +151,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
// Determine alignedness of mtvt
// mtvt[31:N] holds mtvt table entry
// mtvt[N-1:0] is tied to zero.
localparam int unsigned MTVT_LSB = ((SMCLIC_ID_WIDTH + 2) < 6) ? 6 : (SMCLIC_ID_WIDTH + 2);
localparam int unsigned MTVT_LSB = ((CLIC_ID_WIDTH + 2) < 6) ? 6 : (CLIC_ID_WIDTH + 2);
localparam int unsigned MTVT_ADDR_WIDTH = 32 - MTVT_LSB;

logic clk; // Gated clock
Expand Down Expand Up @@ -339,15 +339,15 @@ module cv32e40x_core import cv32e40x_pkg::*;
logic [7:0] irq_clic_level;
logic [1:0] irq_clic_priv;
logic mnxti_irq_pending;
logic [SMCLIC_ID_WIDTH-1:0] mnxti_irq_id;
logic [CLIC_ID_WIDTH-1:0] mnxti_irq_id;
logic [7:0] mnxti_irq_level;

// Used (only) by verification environment
logic irq_ack;
logic [9:0] irq_id;
logic [7:0] irq_level; // Only applicable if SMCLIC = 1
logic [1:0] irq_priv; // Only applicable if SMCLIC = 1
logic irq_shv; // Only applicable if SMCLIC = 1
logic [7:0] irq_level; // Only applicable if CLIC = 1
logic [1:0] irq_priv; // Only applicable if CLIC = 1
logic irq_shv; // Only applicable if CLIC = 1
logic dbg_ack;

// eXtension interface signals
Expand Down Expand Up @@ -456,8 +456,8 @@ module cv32e40x_core import cv32e40x_pkg::*;
.PMA_NUM_REGIONS ( PMA_NUM_REGIONS ),
.PMA_CFG ( PMA_CFG ),
.MTVT_ADDR_WIDTH ( MTVT_ADDR_WIDTH ),
.SMCLIC ( SMCLIC ),
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
.CLIC ( CLIC ),
.CLIC_ID_WIDTH ( CLIC_ID_WIDTH ),
.ZC_EXT ( ZC_EXT ),
.M_EXT ( M_EXT ),
.DEBUG ( DEBUG ),
Expand Down Expand Up @@ -523,7 +523,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
.M_EXT ( M_EXT ),
.X_EXT ( X_EXT ),
.REGFILE_NUM_READ_PORTS ( REGFILE_NUM_READ_PORTS ),
.SMCLIC ( SMCLIC )
.CLIC ( CLIC )
)
id_stage_i
(
Expand Down Expand Up @@ -794,9 +794,9 @@ module cv32e40x_core import cv32e40x_pkg::*;
.X_MISA ( X_MISA ),
.X_ECS_XS ( X_ECS_XS ),
.ZC_EXT ( ZC_EXT ),
.SMCLIC ( SMCLIC ),
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
.SMCLIC_INTTHRESHBITS ( SMCLIC_INTTHRESHBITS ),
.CLIC ( CLIC ),
.CLIC_ID_WIDTH ( CLIC_ID_WIDTH ),
.CLIC_INTTHRESHBITS ( CLIC_INTTHRESHBITS ),
.DEBUG ( DEBUG ),
.DBG_NUM_TRIGGERS ( DBG_NUM_TRIGGERS ),
.NUM_MHPMCOUNTERS ( NUM_MHPMCOUNTERS ),
Expand Down Expand Up @@ -891,8 +891,8 @@ module cv32e40x_core import cv32e40x_pkg::*;
.X_EXT ( X_EXT ),
.A_EXT ( A_EXT ),
.REGFILE_NUM_READ_PORTS ( REGFILE_NUM_READ_PORTS ),
.SMCLIC ( SMCLIC ),
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
.CLIC ( CLIC ),
.CLIC_ID_WIDTH ( CLIC_ID_WIDTH ),
.DEBUG ( DEBUG )
)
controller_i
Expand Down Expand Up @@ -1013,12 +1013,12 @@ module cv32e40x_core import cv32e40x_pkg::*;
////////////////////////////////////////////////////////////////////////

generate
if (SMCLIC) begin : gen_clic_interrupt
if (CLIC) begin : gen_clic_interrupt
assign mip = '0;

cv32e40x_clic_int_controller
#(
.SMCLIC_ID_WIDTH (SMCLIC_ID_WIDTH)
.CLIC_ID_WIDTH (CLIC_ID_WIDTH)
)
clic_int_controller_i
(
Expand Down
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