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Fix for issue #745 #775

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silabs-oysteink
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Refactored debug_cause decision.

1: Removed large ternary debug_cause assignment, replaced by priority between synchronous debug causes only.
2: Moved most priority logic into FSM, setting debug_cause_n whenever ctrl_fsm_ns == DEBUG_TAKEN.

…y logic into the FSM.

SEC clean.

Signed-off-by: Oystein Knauserud <[email protected]>
…ld get the wrong debug_cause. This would happen if a synchronous debug reason was in WB at the same time, the taken NMI/interrupt would kill WB but that was not reflected in the debug cause.

Signed-off-by: Oystein Knauserud <[email protected]>
…pt + single step.

SEC clean if an ebreak with dcsr.ebreakm is not flagged as an exception. Bugfix for not flagging ebreak as exception if dcsr.ebreakm is set will come in a separate PR.

Signed-off-by: Oystein Knauserud <[email protected]>
@silabs-oysteink silabs-oysteink added the Component:RTL For issues in the RTL (e.g. for files in the rtl directory) label Feb 6, 2023
@@ -493,6 +496,8 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*;
assign sync_debug_allowed = !xif_in_wb;

// Debug pending for any other synchronous reason than single step
// Note that the WB stage may be killed for interrupts and NMIs, thus invalidating the instruction causing the sync debug entry.
// Exception triggers to not set pending_sync_debug, as they need to take the single step path through the FSM.
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@Silabs-ArjanB Silabs-ArjanB Feb 6, 2023

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to -> do
"as they need to take the single step path through the FSM": Why? (Add the reasoningnear line 1046; there are comments there, but they don't give me a high level reason why exception triggers are special)

…ingle step debug entry in the controller FSM.

Signed-off-by: Oystein Knauserud <[email protected]>
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Merging in spite of failing ECA check as Øystein Knauserud is actually covered by the requested legal agreement.

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2 participants