User manual updates for mnxti and debug_req_i descriptions #731
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Updated description of legal CSR instruction for accessing the mnxti CSR. Signed-off-by: Oystein Knauserud <[email protected]>
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Dec 14, 2022
docs/user_manual/source/debug.rst
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| @@ -81,7 +81,8 @@ Interface | |||
| | ``dm_exception_addr_i[31:0]`` | input | Address for debugger exception entry | | |||
| +-------------------------------+-----------+--------------------------------------------+ | |||
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| ``debug_req_i`` is the "debug interrupt", issued by the debug module when the core should enter Debug Mode. The ``debug_req_i`` is synchronous to ``clk_i`` and requires a minimum assertion of one clock period to enter Debug Mode. The instruction being decoded during the same cycle that ``debug_req_i`` is first asserted shall not be executed before entering Debug Mode. | |||
| ``debug_req_i`` is the "debug interrupt", issued by the debug module when the core should enter Debug Mode. The ``debug_req_i`` is synchronous to ``clk_i``, level sensitive and requires a minimum assertion of one clock period to enter Debug Mode. | |||
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The debug_req_i is synchronous to clk_i, level sensitive and requires a minimum assertion of one clock period to enter Debug Mode.
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The debug_req_i is synchronous to clk_i and is level sensitive.
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Updated description of the debug_req_i signal.
Updated description of legal CSR instruction for accessing the mnxti CSR.
Signed-off-by: Oystein Knauserud [email protected]