Fix for issue #341. #725
Fix for issue #341. #725
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Removed sticky debug request (debug_req_q) Updated assertion a_fencei_hndshk_req_when_fencei_wb to accomodate changes. Signed-off-by: Oystein Knauserud <[email protected]>
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added
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Component:RTL
| // that can currently cause a deadlock if debug_req_i gets asserted while in debug mode, as | ||
| // a pending but not allowed async debug will cause the ID stage to halt forever while trying | ||
| // to get to an interruptible state. | ||
| assign pending_async_debug = debug_req_i && !debug_mode_q; |
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Remove clk_ungated_i from this module as well as it is no longer needed here
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Removed ungated clock from controller.
| @@ -244,9 +244,10 @@ module cv32e40x_controller_fsm_sva | |||
| else `uvm_error("controller", "Fencei request when no fencei in writeback") | |||
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| // Assert that the fencei request is set the cycle after fencei instruction enters WB (if fencei_ready=1 and there are no higher priority events) | |||
| // Only check when no higher priority event is pending (nmi, async debug or interrupts) and WB stage is not killed | |||
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Can you explain why this assertion was required to be changed?
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When debug_req_q was still in the controller, it would remain set until we actually entered debug mode (causing pending_async_debug to be 1). That would cause the antecedent of the assertion not to trig. Now that the sticky debug is gone, we may go to DEBUG_TAKEN due to a short pulse on debug_req_i and pending_async_debug may be 0 while in the DEBUG_TAKEN state. We are then killing the WB stage, but the antecedent didn't take killing of WB into account and only looked at signals originating from the ex_wb_pipe.
Signed-off-by: Oystein Knauserud <[email protected]>
Removed sticky debug request (debug_req_q)
Updated assertion a_fencei_hndshk_req_when_fencei_wb to accomodate changes.
Signed-off-by: Oystein Knauserud [email protected]