(Partial) fix for issue #325. #650
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Halting EX stage if a CSR write in WB may enable interrupts and at the same time there is an LSU instruction in EX. Fix implemented for both CLIC and basic interrupt mode. Issue can still occur when X_EXT=1. Fixing this would also need several other fixes for the X-interface. Signed-off-by: Oystein Knauserud <[email protected]>
Silabs-ArjanB
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Component:RTL
Silabs-ArjanB
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Aug 25, 2022
rtl/cv32e40x_cs_registers.sv
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| @@ -93,6 +93,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; | |||
| input logic [7:0] mnxti_irq_level_i, | |||
| output logic clic_pa_valid_o, // CSR read data is an address to a function pointer | |||
| output logic [31:0] clic_pa_o, // Address to CLIC function pointer | |||
| output logic csr_irq_enable_write_o, // An irq enable write is being performed in WB (mie or mstatus.mie) | |||
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Remove '(mie or mstatus.mie)' as it is not accurate for CLIC
Signed-off-by: Oystein Knauserud <[email protected]>
Silabs-ArjanB
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Aug 25, 2022
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Halting EX stage if a CSR write in WB may enable interrupts and at the same time there is an LSU instruction in EX. Fix implemented for both CLIC and basic interrupt mode.
Issue can still occur when X_EXT=1. Fixing this would also need several other fixes for the X-interface.
Signed-off-by: Oystein Knauserud [email protected]