Added a 'first_op' to track the first operation of multi operation in… #605
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…structions through the pipeline. RVFI will now only latch rs1/2_rdata when the first operation of a multi operation instruction is in the ID stage. Added assertions to check that jump targets are stable when remaining in ID for multiple cycles. Added assertion to check that RVFI may use operand_a_fw also for JALR instructions, although JALR uses a different bypass mux in RTL. SEC clean. Signed-off-by: Oystein Knauserud <[email protected]>
Silabs-ArjanB
requested changes
Jun 30, 2022
| @@ -256,7 +256,8 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*; | |||
| // Blocking on branch_taken_q, as a jump has already been taken | |||
| assign jump_taken_id = jump_in_id && !branch_taken_q; | |||
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| // todo: RVFI does not use jump_taken_id (which is not in itself an issue); we should have an assertion showing that the target address remains constant during jump_in_id; same remark for branches | |||
| // Note: RVFI does not use jump_taken_id (which is not in itself an issue); An assertion in id_stage_sva checks that the jump target remains stable; | |||
| // todo: Do we need a similar stability check for branches? | |||
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Yes; just add it now (will be less work than picking it up a month from now)
rtl/cv32e40x_core.sv
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| @@ -238,6 +238,9 @@ module cv32e40x_core import cv32e40x_pkg::*; | |||
| logic lsu_valid_wb; | |||
| logic lsu_ready_1; | |||
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| logic lsu_first_op_ex; | |||
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Move signals to between line 226 and 227
rtl/cv32e40x_if_stage.sv
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| @@ -123,7 +123,8 @@ module cv32e40x_if_stage import cv32e40x_pkg::*; | |||
| // eXtension interface signals | |||
| logic [X_ID_WIDTH-1:0] xif_id; | |||
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| // Flag for last operation - used by Zc* | |||
| // Flag for first and last operation - used by Zc* | |||
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Remove used by Zc* comment (it is more general (I hope at least))
rtl/cv32e40x_if_stage.sv
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| assign seq_instr = '0; | ||
| assign seq_ready = 1'b1; | ||
| assign seq_first = 1'b1; |
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Probably it won't matter much, but I think that seq_first = 1'b0 is a more logical default if there is no sequencer
rtl/cv32e40x_load_store_unit.sv
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| @@ -52,6 +52,8 @@ module cv32e40x_load_store_unit import cv32e40x_pkg::*; | |||
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| // Stage 0 outputs (EX) | |||
| output logic lsu_split_0_o, // Misaligned access is split in two transactions (to controller) | |||
| output logic lsu_first_op_0_o, // First operation is active in EX | |||
| @@ -387,6 +389,9 @@ module cv32e40x_load_store_unit import cv32e40x_pkg::*; | |||
| end | |||
| end | |||
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| assign lsu_last_op_0_o = !lsu_split_0_o; | |||
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Add comment that these signals are only valid when lsu_en = 1 (I think)
| @@ -125,5 +135,27 @@ module cv32e40x_id_stage_sva | |||
| $onehot0({alu_en, div_en, mul_en, csr_en, sys_en, lsu_en, xif_en})) | |||
| else `uvm_error("id_stage", "Multiple functional units enabled") | |||
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| // Assert that jalr_fw has the same value as operand_a_fw when a jump is taken | |||
| // Only checking for JALR, as regular JAL do not use any RF or bypass operands for the jump target. | |||
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Add reason why this needs to be checked (i.e. because RVFI uses alu_jmpr instead of operand_a_fw)
Signed-off-by: Oystein Knauserud <[email protected]>
Silabs-ArjanB
approved these changes
Jul 1, 2022
Silabs-ArjanB
added
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Component:RTL
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…structions through the pipeline.
RVFI will now only latch rs1/2_rdata when the first operation of a multi operation instruction is in the ID stage.
Added assertions to check that jump targets are stable when remaining in ID for multiple cycles.
Added assertion to check that RVFI may use operand_a_fw also for JALR instructions, although JALR uses a different bypass mux in RTL.
SEC clean.
Signed-off-by: Oystein Knauserud [email protected]