Unifying interrupt controllers; aligning cs registers syntax with cor… #566
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…e level Signed-off-by: Arjan Bink <[email protected]>
Silabs-ArjanB
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Jun 3, 2022
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…e level
SEC clean for SMCLIC =0 and SMCLIC =1 (if clic_irq_priv_i = 2'b11)
Do NOT merge into the CV32E40S (will have a separate/similar PR).
Signed-off-by: Arjan Bink [email protected]