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Corrected RW into WARL for mseccfg.RLB, mseccfg.MMWP, mseccfg.MML, pm… #529

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May 5, 2022
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Corrected RW into WARL for mseccfg.RLB, mseccfg.MMWP, mseccfg.MML, pm… #529

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103 changes: 52 additions & 51 deletions docs/user_manual/source/control_status_registers.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -298,6 +298,8 @@ level):
operation of the core.

* **WARL**: **write-any-read-legal** fields store only legal values written by CSR writes.
The WARL keyword can optionally be followed by a legal value (or comma separated list of legal values) enclosed in brackets.
If the legal value(s) are not specified, then all possible values are considered valid.
For example, a WARL (0x0) field supports only the value 0x0. Any value may be written, but
all reads would return 0x0 regardless of the value being written to it. A WARL field may
support more than one value. If an unsupported value is (attempted to be) written to a WARL field, the original (legal) value
Expand Down Expand Up @@ -615,7 +617,7 @@ Detailed:
+---------+------------------+---------------------------------------------------------------------------------------------------------------+
| Bit # | R/W | Description |
+=========+==================+===============================================================================================================+
| 31:7 | RW | **BASE[31:7]**: Trap-handler base address, always aligned to 128 bytes. |
| 31:7 | WARL | **BASE[31:7]**: Trap-handler base address, always aligned to 128 bytes. |
+---------+------------------+---------------------------------------------------------------------------------------------------------------+
| 6:2 | WARL (0x0) | **BASE[6:2]**: Trap-handler base address, always aligned to 128 bytes. ``mtvec[6:2]`` is hardwired to 0x0. |
+---------+------------------+---------------------------------------------------------------------------------------------------------------+
Expand Down Expand Up @@ -647,7 +649,7 @@ Detailed:
+---------+------------------+---------------------------------------------------------------------------------------------------------------+
| Bit # | R/W | Description |
+=========+==================+===============================================================================================================+
| 31:7 | RW | **BASE[31:7]**: Trap-handler base address, always aligned to 128 bytes. |
| 31:7 | WARL | **BASE[31:7]**: Trap-handler base address, always aligned to 128 bytes. |
+---------+------------------+---------------------------------------------------------------------------------------------------------------+
| 6:2 | WARL (0x0) | **BASE[6:2]**: Trap-handler base address, always aligned to 128 bytes. ``mtvec[6:2]`` is hardwired to 0x0. |
+---------+------------------+---------------------------------------------------------------------------------------------------------------+
Expand Down Expand Up @@ -1829,11 +1831,11 @@ Detailed:
+------+-------------+-----------------------------------------------------------------------------------------------------------------------------------+
| 7:3 | WPRI (0x0) | Hardwired to 0. |
+------+-------------+-----------------------------------------------------------------------------------------------------------------------------------+
| 2 | RW | **RLB**. Rule Locking Bypass. |
| 2 | WARL | **RLB**. Rule Locking Bypass. |
+------+-------------+-----------------------------------------------------------------------------------------------------------------------------------+
| 1 | RW | **MMWP**. Machine Mode Whitelist Policy. This is a sticky bit and once set can only be unset due to ``rst_ni`` assertion. |
| 1 | WARL | **MMWP**. Machine Mode Whitelist Policy. This is a sticky bit and once set can only be unset due to ``rst_ni`` assertion. |
+------+-------------+-----------------------------------------------------------------------------------------------------------------------------------+
| 0 | RW | **MML**. Machine Mode Lockdown. This is a sticky bit and once set can only be unset due to ``rst_ni`` assertion. |
| 0 | WARL | **MML**. Machine Mode Lockdown. This is a sticky bit and once set can only be unset due to ``rst_ni`` assertion. |
+------+-------------+-----------------------------------------------------------------------------------------------------------------------------------+

Machine Security Configuration (``mseccfgh``)
Expand All @@ -1860,62 +1862,60 @@ Detailed:

Detailed ``pmpcfg0``:

+-------+-----------------+---------------------------------------------------------------------------------------------------------------+
| Bit# | R/W | Definition |
+=======+=================+===============================================================================================================+
| 31:24 | RW | PMP3CFG |
+-------+-----------------+---------------------------------------------------------------------------------------------------------------+
| 23:16 | RW | PMP2CFG |
+-------+-----------------+---------------------------------------------------------------------------------------------------------------+
| 15:8 | RW | PMP1CFG |
+-------+-----------------+---------------------------------------------------------------------------------------------------------------+
| 7:0 | RW | PMP0CFG |
+-------+-----------------+---------------------------------------------------------------------------------------------------------------+
+-------+---------------+
| Bit# | Definition |
+=======+===============+
| 31:24 | PMP3CFG |
+-------+---------------+
| 23:16 | PMP2CFG |
+-------+---------------+
| 15:8 | PMP1CFG |
+-------+---------------+
| 7:0 | PMP0CFG |
+-------+---------------+

Detailed ``pmpcfg1``:

+-------+------------------+---------------------------------------------------------------------------------------------------------------+
| Bit# | R/W | Definition |
+=======+==================+===============================================================================================================+
| 31:24 | RW | PMP7CFG |
+-------+------------------+---------------------------------------------------------------------------------------------------------------+
| 23:16 | RW | PMP6CFG |
+-------+------------------+---------------------------------------------------------------------------------------------------------------+
| 15:8 | RW | PMP5CFG |
+-------+------------------+---------------------------------------------------------------------------------------------------------------+
| 7:0 | RW | PMP4CFG |
+-------+------------------+---------------------------------------------------------------------------------------------------------------+
+-------+---------------+
| Bit# | Definition |
+=======+===============+
| 31:24 | PMP7CFG |
+-------+---------------+
| 23:16 | PMP6CFG |
+-------+---------------+
| 15:8 | PMP5CFG |
+-------+---------------+
| 7:0 | PMP4CFG |
+-------+---------------+

...

Detailed ``pmpcfg15``:

+-------+------------------+---------------------------------------------------------------------------------------------------------------+
| Bit# | R/W | Definition |
+=======+==================+===============================================================================================================+
| 31:24 | RW | PMP63CFG |
+-------+------------------+---------------------------------------------------------------------------------------------------------------+
| 23:16 | RW | PMP62CFG |
+-------+------------------+---------------------------------------------------------------------------------------------------------------+
| 15:8 | RW | PMP61CFG |
+-------+------------------+---------------------------------------------------------------------------------------------------------------+
| 7:0 | RW | PMP60CFG |
+-------+------------------+---------------------------------------------------------------------------------------------------------------+
+-------+---------------+
| Bit# | Definition |
+=======+===============+
| 31:24 | PMP63CFG |
+-------+---------------+
| 23:16 | PMP62CFG |
+-------+---------------+
| 15:8 | PMP61CFG |
+-------+---------------+
| 7:0 | PMP60CFG |
+-------+---------------+

The configuration fields for each ``pmpxcfg`` are as follows:

+-------+------------------+---------------------------+
| Bit# | R/W | Definition |
+=======+==================+===========================+
| 8 | WARL (0x0) | Reserved |
+-------+------------------+---------------------------+
| 7 | RW | **L**. Lock |
| 7 | WARL | **L**. Lock |
+-------+------------------+---------------------------+
| 6:5 | WARL (0x0) | Reserved |
+-------+------------------+---------------------------+
| 4:3 | RW | **A**. Mode |
| 4:3 | WARL | **A**. Mode |
+-------+------------------+---------------------------+
| 2 | RW / | **X**. Execute permission |
| 2 | WARL / | **X**. Execute permission |
+-------+ WARL (0x0, 0x1, +---------------------------+
| 1 | 0x3, 0x4, | **W**. Write permission |
+-------+ 0x5, 0x7) +---------------------------+
Expand All @@ -1926,8 +1926,9 @@ Detailed:
pmpxcfg is WARL (0x0) if x >= ``PMP_NUM_REGIONS``.

.. note::
The **R**, **W** and **X** together form a collective WARL field for which the combinations with **R** = 0 and **W** = 1 are reserved for future use
if **mseccfg.MML** = 0. The value of the collective **R**, **W**, **X** bitfield will remain unchanged when attempting to write **R** = 0 and **W** = 1 while **mseccfg.MML** = 0.
If **mseccfg.MML** = 0, then the **R**, **W** and **X** together form a collective WARL field for which the combinations with **R** = 0 and **W** = 1 are reserved for future use
The value of the collective **R**, **W**, **X** bitfield will remain unchanged when attempting to write **R** = 0 and **W** = 1 while **mseccfg.MML** = 0.
If **mseccfg.MML** = 1, then the **R**, **W** and **X** together form a collective WARL field in which all values are valid.

PMP Address (``pmpaddr0`` - ``pmpaddr63``)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Expand All @@ -1936,13 +1937,13 @@ Detailed:

Reset Value: defined (based on ``PMP_PMPADDR_RV[]``)

+-------+------------------+---------------------------+
| Bit# | R/W | Definition |
+=======+==================+===========================+
| 31:0 | RW / WARL (0x0) | ADDRESS[33:2] |
+-------+------------------+---------------------------+
+-------+-----------------------+---------------------------+
| Bit# | R/W | Definition |
+=======+=======================+===========================+
| 31:0 | WARL / WARL (0x0) | ADDRESS[33:2] |
+-------+-----------------------+---------------------------+

pmpaddrx is RW if x < ``PMP_NUM_REGIONS`` and WARL (0x0) otherwise.
pmpaddrx is WARL if x < ``PMP_NUM_REGIONS`` and WARL (0x0) otherwise.

.. only:: ZICNTR

Expand Down