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Currently, a CLIC pointer that arrives in WB will not signal wb_valid, and RVFI is not notified of the pointer.
Similarly, split LSU accesses only signal wb_valid for the last operation, not the first.
Wb_valid should be set for all cycles where a valid instruction or part of an instruction is done in WB (similar to id_valid and ex_valid for instance). RVFI would need to adapt to this by for instance checking the 'last' bit inside it's pipeline model.
The text was updated successfully, but these errors were encountered:
Currently, a CLIC pointer that arrives in WB will not signal wb_valid, and RVFI is not notified of the pointer.
Similarly, split LSU accesses only signal wb_valid for the last operation, not the first.
Wb_valid should be set for all cycles where a valid instruction or part of an instruction is done in WB (similar to id_valid and ex_valid for instance). RVFI would need to adapt to this by for instance checking the 'last' bit inside it's pipeline model.
The text was updated successfully, but these errors were encountered: