feat(build): Add 32bits RTE header files for x86 and arm (#36)

* feat(build): Add 32bits RTE header files for x86 and arm Signed-off-by: wangzihao <[email protected]>
openebs-archive · Dec 11, 2019 · c8888bf · c8888bf
1 parent 2e5a5b2
commit c8888bf
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Showing 10 changed files with 301 additions and 4 deletions.
diff --git a/include/arch/arm/Makefile.am b/include/arch/arm/Makefile.am
@@ -1,7 +1,9 @@
 HEADER_H = \
 	$(top_srcdir)/include/arch/arm/rte_atomic.h	\
+	$(top_srcdir)/include/arch/arm/rte_atomic_32.h	\
 	$(top_srcdir)/include/arch/arm/rte_atomic_64.h	\
 	$(top_srcdir)/include/arch/arm/rte_pause.h	\
+	$(top_srcdir)/include/arch/arm/rte_pause_32.h
 	$(top_srcdir)/include/arch/arm/rte_pause_64.h
 
 libcstordir = $(includedir)/libcstor/arch/arm

diff --git a/include/arch/arm/rte_atomic.h b/include/arch/arm/rte_atomic.h
@@ -5,6 +5,10 @@
 #ifndef _RTE_ATOMIC_ARM_H_
 #define _RTE_ATOMIC_ARM_H_
 
+#if defined(__aarch64__)
 #include <arch/arm/rte_atomic_64.h>
+#else
+#include <arch/arm/rte_atomic_32.h>
+#endif
 
 #endif /* _RTE_ATOMIC_ARM_H_ */
diff --git a/include/arch/arm/rte_atomic_32.h b/include/arch/arm/rte_atomic_32.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ */
+
+#ifndef _RTE_ATOMIC_ARM32_H_
+#define _RTE_ATOMIC_ARM32_H_
+
+/*
+ *  Platform must be built with CONFIG_RTE_FORCE_INTRINSICS
+ */
+#ifndef RTE_FORCE_INTRINSICS
+#define RTE_FORCE_INTRINSICS
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_atomic.h"
+
+#define	rte_mb()  __sync_synchronize()
+
+#define	rte_wmb() do { asm volatile ("dmb st" : : : "memory"); } while (0)
+
+#define	rte_rmb() __sync_synchronize()
+
+#define rte_smp_mb() rte_mb()
+
+#define rte_smp_wmb() rte_wmb()
+
+#define rte_smp_rmb() rte_rmb()
+
+#define rte_io_mb() rte_mb()
+
+#define rte_io_wmb() rte_wmb()
+
+#define rte_io_rmb() rte_rmb()
+
+#define rte_cio_wmb() rte_wmb()
+
+#define rte_cio_rmb() rte_rmb()
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_ATOMIC_ARM32_H_ */
diff --git a/include/arch/arm/rte_pause.h b/include/arch/arm/rte_pause.h
@@ -9,7 +9,11 @@
 extern "C" {
 #endif
 
+#if defined(__aarch64__)
 #include <arch/arm/rte_pause_64.h>
+#else
+#include <arch/arm/rte_pause_32.h>
+#endif
 
 #ifdef __cplusplus
 }

diff --git a/include/arch/arm/rte_pause_32.h b/include/arch/arm/rte_pause_32.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#ifndef _RTE_PAUSE_ARM32_H_
+#define _RTE_PAUSE_ARM32_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include "generic/rte_pause.h"
+
+static inline void rte_pause(void)
+{
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_PAUSE_ARM32_H_ */
diff --git a/include/arch/x86/Makefile.am b/include/arch/x86/Makefile.am
@@ -1,5 +1,6 @@
 HEADER_H = \
 	$(top_srcdir)/include/arch/x86/rte_atomic_64.h	\
+	$(top_srcdir)/include/arch/x86/rte_atomic_32.h	\
 	$(top_srcdir)/include/arch/x86/rte_atomic.h		\
 	$(top_srcdir)/include/arch/x86/rte_pause.h
 

diff --git a/include/arch/x86/rte_atomic.h b/include/arch/x86/rte_atomic.h
@@ -216,9 +216,9 @@ static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
 }
 #endif
 
-#ifdef RTE_ARCH_I686
+#if defined(__i686__)
 #include "arch/x86/rte_atomic_32.h"
-#else
+#elif defined(__x86_64__)
 #include "arch/x86/rte_atomic_64.h"
 #endif
 

diff --git a/include/arch/x86/rte_atomic_32.h b/include/arch/x86/rte_atomic_32.h
@@ -0,0 +1,214 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2014 Intel Corporation.
+ */
+
+/*
+ * Inspired from FreeBSD src/sys/i386/include/atomic.h
+ * Copyright (c) 1998 Doug Rabson
+ * All rights reserved.
+ */
+
+#ifndef _RTE_ATOMIC_X86_H_
+#error do not include this file directly, use <rte_atomic.h> instead
+#endif
+
+#ifndef _RTE_ATOMIC_I686_H_
+#define _RTE_ATOMIC_I686_H_
+
+#include <stdint.h>
+#include <rte_common.h>
+#include <arch/x86/rte_atomic.h>
+
+/*------------------------- 64 bit atomic operations -------------------------*/
+
+#ifndef RTE_FORCE_INTRINSICS
+static inline int
+rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
+{
+	uint8_t res;
+	RTE_STD_C11
+	union {
+		struct {
+			uint32_t l32;
+			uint32_t h32;
+		};
+		uint64_t u64;
+	} _exp, _src;
+
+	_exp.u64 = exp;
+	_src.u64 = src;
+
+#ifndef __PIC__
+    asm volatile (
+            MPLOCKED
+            "cmpxchg8b (%[dst]);"
+            "setz %[res];"
+            : [res] "=a" (res)      /* result in eax */
+            : [dst] "S" (dst),      /* esi */
+             "b" (_src.l32),       /* ebx */
+             "c" (_src.h32),       /* ecx */
+             "a" (_exp.l32),       /* eax */
+             "d" (_exp.h32)        /* edx */
+			: "memory" );           /* no-clobber list */
+#else
+	asm volatile (
+            "xchgl %%ebx, %%edi;\n"
+			MPLOCKED
+			"cmpxchg8b (%[dst]);"
+			"setz %[res];"
+            "xchgl %%ebx, %%edi;\n"
+			: [res] "=a" (res)      /* result in eax */
+			: [dst] "S" (dst),      /* esi */
+			  "D" (_src.l32),       /* ebx */
+			  "c" (_src.h32),       /* ecx */
+			  "a" (_exp.l32),       /* eax */
+			  "d" (_exp.h32)        /* edx */
+			: "memory" );           /* no-clobber list */
+#endif
+
+	return res;
+}
+
+static inline uint64_t
+rte_atomic64_exchange(volatile uint64_t *dest, uint64_t val)
+{
+	uint64_t old;
+
+	do {
+		old = *dest;
+	} while (rte_atomic64_cmpset(dest, old, val) == 0);
+
+	return old;
+}
+
+static inline void
+rte_atomic64_init(rte_atomic64_t *v)
+{
+	int success = 0;
+	uint64_t tmp;
+
+	while (success == 0) {
+		tmp = v->cnt;
+		success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
+		                              tmp, 0);
+	}
+}
+
+static inline int64_t
+rte_atomic64_read(rte_atomic64_t *v)
+{
+	int success = 0;
+	uint64_t tmp;
+
+	while (success == 0) {
+		tmp = v->cnt;
+		/* replace the value by itself */
+		success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
+		                              tmp, tmp);
+	}
+	return tmp;
+}
+
+static inline void
+rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
+{
+	int success = 0;
+	uint64_t tmp;
+
+	while (success == 0) {
+		tmp = v->cnt;
+		success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
+		                              tmp, new_value);
+	}
+}
+
+static inline void
+rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
+{
+	int success = 0;
+	uint64_t tmp;
+
+	while (success == 0) {
+		tmp = v->cnt;
+		success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
+		                              tmp, tmp + inc);
+	}
+}
+
+static inline void
+rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
+{
+	int success = 0;
+	uint64_t tmp;
+
+	while (success == 0) {
+		tmp = v->cnt;
+		success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
+		                              tmp, tmp - dec);
+	}
+}
+
+static inline void
+rte_atomic64_inc(rte_atomic64_t *v)
+{
+	rte_atomic64_add(v, 1);
+}
+
+static inline void
+rte_atomic64_dec(rte_atomic64_t *v)
+{
+	rte_atomic64_sub(v, 1);
+}
+
+static inline int64_t
+rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
+{
+	int success = 0;
+	uint64_t tmp;
+
+	while (success == 0) {
+		tmp = v->cnt;
+		success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
+		                              tmp, tmp + inc);
+	}
+
+	return tmp + inc;
+}
+
+static inline int64_t
+rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
+{
+	int success = 0;
+	uint64_t tmp;
+
+	while (success == 0) {
+		tmp = v->cnt;
+		success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
+		                              tmp, tmp - dec);
+	}
+
+	return tmp - dec;
+}
+
+static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
+{
+	return rte_atomic64_add_return(v, 1) == 0;
+}
+
+static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
+{
+	return rte_atomic64_sub_return(v, 1) == 0;
+}
+
+static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
+{
+	return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
+}
+
+static inline void rte_atomic64_clear(rte_atomic64_t *v)
+{
+	rte_atomic64_set(v, 0);
+}
+#endif
+
+#endif /* _RTE_ATOMIC_I686_H_ */
diff --git a/include/generic/rte_atomic.h b/include/generic/rte_atomic.h
@@ -35,8 +35,10 @@
 #define _RTE_ATOMIC_H_
 
 #ifndef RTE_FORCE_INTRINSICS
+#if defined(__aarch64__) || defined(__arm__)
 #define RTE_FORCE_INTRINSICS
 #endif
+#endif
 /**
  * @file
  * Atomic Operations

diff --git a/include/rte_ring.h b/include/rte_ring.h
@@ -99,10 +99,10 @@ extern "C" {
 #include <rte_memory.h>
 #include <generic/rte_atomic.h>
 
-#if defined(__x86_64__)
+#if defined(__x86_64__) || defined(__i686__)
 #include <arch/x86/rte_pause.h>
 #include <arch/x86/rte_atomic.h>
-#elif defined(__aarch64__)
+#elif defined(__aarch64__) || defined(__arm__)
 #include <arch/arm/rte_pause.h>
 #include <arch/arm/rte_atomic.h>
 #endif