feat(build): add rte header files to support building on aarch64 (#35)

Related to: openebs/openebs#1295 openebs-archive/maya#1493

Signed-off-by: wangzihao <[email protected]>

configure.ac

@@ -34,6 +34,9 @@ AC_CONFIG_FILES([
                  src/Makefile
                  include/Makefile
                  include/sys/Makefile
+                 include/generic/Makefile
+                 include/arch/x86/Makefile
+                 include/arch/arm/Makefile
 ])
 
 AC_OUTPUT

include/Makefile.am

@@ -1,16 +1,12 @@
-SUBDIRS = sys
+SUBDIRS = sys generic arch/arm arch/x86
 
 HEADER_H = \
 	$(top_srcdir)/include/data_conn.h	\
 	$(top_srcdir)/include/gtest_utils.h	\
 	$(top_srcdir)/include/libuzfs.h	\
 	$(top_srcdir)/include/mgmt_conn.h	\
-	$(top_srcdir)/include/rte_atomic_64.h	\
-	$(top_srcdir)/include/rte_atomic_generic.h	\
-	$(top_srcdir)/include/rte_atomic.h	\
 	$(top_srcdir)/include/rte_common.h	\
 	$(top_srcdir)/include/rte_memory.h	\
-	$(top_srcdir)/include/rte_pause.h	\
 	$(top_srcdir)/include/rte_ring.h	\
 	$(top_srcdir)/include/uzfs_io.h	\
 	$(top_srcdir)/include/uzfs_mgmt.h	\

include/arch/arm/Makefile.am

@@ -0,0 +1,9 @@
+HEADER_H = \
+	$(top_srcdir)/include/arch/arm/rte_atomic.h	\
+	$(top_srcdir)/include/arch/arm/rte_atomic_64.h	\
+	$(top_srcdir)/include/arch/arm/rte_pause.h	\
+	$(top_srcdir)/include/arch/arm/rte_pause_64.h
+
+libcstordir = $(includedir)/libcstor/arch/arm
+libcstor_HEADERS = $(HEADER_H)
+

include/arch/arm/rte_atomic.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ */
+
+#ifndef _RTE_ATOMIC_ARM_H_
+#define _RTE_ATOMIC_ARM_H_
+
+#include <arch/arm/rte_atomic_64.h>
+
+#endif /* _RTE_ATOMIC_ARM_H_ */

include/arch/arm/rte_atomic_64.h

@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015 Cavium, Inc
+ * Copyright(c) 2019 Arm Limited
+ */
+
+#ifndef _RTE_ATOMIC_ARM64_H_
+#define _RTE_ATOMIC_ARM64_H_
+
+/*
+ *  Platform must be built with CONFIG_RTE_FORCE_INTRINSICS
+ */
+#ifndef RTE_FORCE_INTRINSICS
+#define RTE_FORCE_INTRINSICS
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_atomic.h"
+
+#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
+#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
+
+#define rte_mb() dsb(sy)
+
+#define rte_wmb() dsb(st)
+
+#define rte_rmb() dsb(ld)
+
+#define rte_smp_mb() dmb(ish)
+
+#define rte_smp_wmb() dmb(ishst)
+
+#define rte_smp_rmb() dmb(ishld)
+
+#define rte_io_mb() rte_mb()
+
+#define rte_io_wmb() rte_wmb()
+
+#define rte_io_rmb() rte_rmb()
+
+#define rte_cio_wmb() dmb(oshst)
+
+#define rte_cio_rmb() dmb(oshld)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_ATOMIC_ARM64_H_ */

include/arch/arm/rte_pause.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#ifndef _RTE_PAUSE_ARM_H_
+#define _RTE_PAUSE_ARM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <arch/arm/rte_pause_64.h>
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_PAUSE_ARM_H_ */

include/arch/arm/rte_pause_64.h

@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#ifndef _RTE_PAUSE_ARM64_H_
+#define _RTE_PAUSE_ARM64_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include "generic/rte_pause.h"
+
+static inline void rte_pause(void)
+{
+	asm volatile("yield" ::: "memory");
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_PAUSE_ARM64_H_ */

include/arch/x86/Makefile.am

@@ -0,0 +1,8 @@
+HEADER_H = \
+	$(top_srcdir)/include/arch/x86/rte_atomic_64.h	\
+	$(top_srcdir)/include/arch/x86/rte_atomic.h		\
+	$(top_srcdir)/include/arch/x86/rte_pause.h
+
+libcstordir = $(includedir)/libcstor/arch/x86
+libcstor_HEADERS = $(HEADER_H)
+

include/rte_atomic.h → include/arch/x86/rte_atomic.h

@@ -217,9 +217,9 @@ static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
 #endif
 
 #ifdef RTE_ARCH_I686
-#include "rte_atomic_32.h"
+#include "arch/x86/rte_atomic_32.h"
 #else
-#include "rte_atomic_64.h"
+#include "arch/x86/rte_atomic_64.h"
 #endif
 
 #ifdef __cplusplus

include/rte_atomic_64.h → include/arch/x86/rte_atomic_64.h

@@ -46,7 +46,7 @@
 
 #include <stdint.h>
 #include <rte_common.h>
-#include <rte_atomic.h>
+#include <arch/x86/rte_atomic.h>
 
 /*------------------------- 64 bit atomic operations -------------------------*/
 

include/generic/Makefile.am

@@ -0,0 +1,6 @@
+HEADER_H = \
+	$(top_srcdir)/include/generic/rte_atomic.h	\
+	$(top_srcdir)/include/generic/rte_pause.h
+
+libcstordir = $(includedir)/libcstor/generic
+libcstor_HEADERS = $(HEADER_H)

include/rte_atomic_generic.h → include/generic/rte_atomic.h

@@ -34,6 +34,9 @@
 #ifndef _RTE_ATOMIC_H_
 #define _RTE_ATOMIC_H_
 
+#ifndef RTE_FORCE_INTRINSICS
+#define RTE_FORCE_INTRINSICS
+#endif
 /**
  * @file
  * Atomic Operations

include/generic/rte_pause.h

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#ifndef _RTE_PAUSE_H_
+#define _RTE_PAUSE_H_
+
+/**
+ * @file
+ *
+ * CPU pause operation.
+ *
+ */
+
+/**
+ * Pause CPU execution for a short while
+ *
+ * This call is intended for tight loops which poll a shared resource or wait
+ * for an event. A short pause within the loop may reduce the power consumption.
+ */
+static inline void rte_pause(void);
+
+#endif /* _RTE_PAUSE_H_ */

include/rte_ring.h

@@ -97,9 +97,15 @@ extern "C" {
 #include <errno.h>
 #include <rte_common.h>
 #include <rte_memory.h>
-#include <rte_pause.h>
-#include <rte_atomic_generic.h>
-#include <rte_atomic.h>
+#include <generic/rte_atomic.h>
+
+#if defined(__x86_64__)
+#include <arch/x86/rte_pause.h>
+#include <arch/x86/rte_atomic.h>
+#elif defined(__aarch64__)
+#include <arch/arm/rte_pause.h>
+#include <arch/arm/rte_atomic.h>
+#endif
 
 #define RTE_TAILQ_RING_NAME "RTE_RING"