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Make more room for hbicore_extended in PNOR layout files.
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-Accomodates extra space required by TLS
-Extended HBI pnor size by 1.5MB for fsp, fake, default and axone layouts.
-Default and axone layouts were already close to max size of 64MB, so
 moved 1.5MB out of PAYLOAD section.
-Removed buffer in front of  EEPROM CACHE section.

Change-Id: I8beb975a3ce8d5bb6170b4e5622757bd963a1727
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72173
Reviewed-by: Nicholas E. Bofferding <[email protected]>
Reviewed-by: Christian R. Geddes <[email protected]>
Tested-by: Jenkins Server <[email protected]>
Tested-by: Jenkins OP Build CI <[email protected]>
Tested-by: Jenkins OP HW <[email protected]>
Tested-by: FSP CI Jenkins <[email protected]>
Reviewed-by: Daniel M. Crowell <[email protected]>
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@milesg-github @dcrowell77
milesg-github authored and dcrowell77 committed Mar 11, 2019
1 parent 4b29a11 commit 676c584
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Showing 4 changed files with 38 additions and 38 deletions.
16 changes: 8 additions & 8 deletions src/build/buildpnor/defaultPnorLayout.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -140,18 +140,18 @@ Layout Description
<ecc/>
</section>
<section>
<description>Hostboot Extended image (12MB w/o ECC)</description>
<description>Hostboot Extended image (15MB)</description>
<eyeCatch>HBI</eyeCatch>
<physicalOffset>0x451000</physicalOffset>
<physicalRegionSize>0xD80000</physicalRegionSize>
<physicalRegionSize>0xF00000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
<ecc/>
</section>
<section>
<description>SBE-IPL (Staging Area) (752K)</description>
<eyeCatch>SBE</eyeCatch>
<physicalOffset>0x11D1000</physicalOffset>
<physicalOffset>0x1351000</physicalOffset>
<physicalRegionSize>0xBC000</physicalRegionSize>
<sha512perEC/>
<sha512Version/>
Expand All @@ -161,7 +161,7 @@ Layout Description
<section>
<description>HCODE Ref Image (1.125MB)</description>
<eyeCatch>HCODE</eyeCatch>
<physicalOffset>0x128D000</physicalOffset>
<physicalOffset>0x140D000</physicalOffset>
<physicalRegionSize>0x120000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
Expand All @@ -170,17 +170,17 @@ Layout Description
<section>
<description>Hostboot Runtime Services for Sapphire (7.0MB)</description>
<eyeCatch>HBRT</eyeCatch>
<physicalOffset>0x13AD000</physicalOffset>
<physicalOffset>0x152D000</physicalOffset>
<physicalRegionSize>0x700000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
<ecc/>
</section>
<section>
<description>Payload (21.375MB)</description>
<description>Payload (19.875MB)</description>
<eyeCatch>PAYLOAD</eyeCatch>
<physicalOffset>0x1AAD000</physicalOffset>
<physicalRegionSize>0x1560000</physicalRegionSize>
<physicalOffset>0x1C2D000</physicalOffset>
<physicalRegionSize>0x13E0000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
<ecc/>
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20 changes: 10 additions & 10 deletions src/build/buildpnor/pnorLayoutAxone.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -139,18 +139,18 @@ Layout Description
<ecc/>
</section>
<section>
<description>Hostboot Extended image (12MB w/o ECC)</description>
<description>Hostboot Extended image (15MB)</description>
<eyeCatch>HBI</eyeCatch>
<physicalOffset>0x451000</physicalOffset>
<physicalRegionSize>0xD80000</physicalRegionSize>
<physicalRegionSize>0xF00000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
<ecc/>
</section>
<section>
<description>SBE-IPL (Staging Area) (752K)</description>
<eyeCatch>SBE</eyeCatch>
<physicalOffset>0x11D1000</physicalOffset>
<physicalOffset>0x1351000</physicalOffset>
<physicalRegionSize>0xBC000</physicalRegionSize>
<sha512perEC/>
<sha512Version/>
Expand All @@ -160,7 +160,7 @@ Layout Description
<section>
<description>HCODE Ref Image (1.125MB)</description>
<eyeCatch>HCODE</eyeCatch>
<physicalOffset>0x128D000</physicalOffset>
<physicalOffset>0x140D000</physicalOffset>
<physicalRegionSize>0x120000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
Expand All @@ -169,17 +169,17 @@ Layout Description
<section>
<description>Hostboot Runtime Services for Sapphire (7.0MB)</description>
<eyeCatch>HBRT</eyeCatch>
<physicalOffset>0x13AD000</physicalOffset>
<physicalOffset>0x152D000</physicalOffset>
<physicalRegionSize>0x700000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
<ecc/>
</section>
<section>
<description>Payload (21.375MB)</description>
<description>Payload (19.875MB)</description>
<eyeCatch>PAYLOAD</eyeCatch>
<physicalOffset>0x1AAD000</physicalOffset>
<physicalRegionSize>0x1560000</physicalRegionSize>
<physicalOffset>0x1C2D000</physicalOffset>
<physicalRegionSize>0x13E0000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
<ecc/>
Expand Down Expand Up @@ -327,15 +327,15 @@ Layout Description
<section>
<description>Eeprom Cache(512K)</description>
<eyeCatch>EECACHE</eyeCatch>
<physicalOffset>0x3E14000</physicalOffset>
<physicalOffset>0x3DF4000</physicalOffset>
<physicalRegionSize>0x80000</physicalRegionSize>
<side>sideless</side>
<ecc/>
</section>
<section>
<description>Ultravisor XSCOM White/Blacklist (64K)</description>
<eyeCatch>UVBWLIST</eyeCatch>
<physicalOffset>0x3E94000</physicalOffset>
<physicalOffset>0x3E74000</physicalOffset>
<physicalRegionSize>0x10000</physicalRegionSize>
<side>sideless</side>
<sha512Version/>
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32 changes: 16 additions & 16 deletions src/build/buildpnor/pnorLayoutFSP.xml
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Expand Up @@ -5,7 +5,7 @@
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2016,2018 -->
<!-- Contributors Listed Below - COPYRIGHT 2016,2019 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
Expand Down Expand Up @@ -140,18 +140,18 @@ Layout Description - Used when building an FSP driver
<ecc/>
</section>
<section>
<description>Hostboot Extended image (12MB w/o ECC)</description>
<description>Hostboot Extended image (15.0MB)</description>
<eyeCatch>HBI</eyeCatch>
<physicalOffset>0x451000</physicalOffset>
<physicalRegionSize>0xD80000</physicalRegionSize>
<physicalRegionSize>0xF00000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
<ecc/>
</section>
<section>
<description>SBE-IPL (Staging Area) (752K)</description>
<eyeCatch>SBE</eyeCatch>
<physicalOffset>0x11D1000</physicalOffset>
<physicalOffset>0x1351000</physicalOffset>
<physicalRegionSize>0xBC000</physicalRegionSize>
<sha512perEC/>
<sha512Version/>
Expand All @@ -161,7 +161,7 @@ Layout Description - Used when building an FSP driver
<section>
<description>HCODE Ref Image (1.125MB)</description>
<eyeCatch>HCODE</eyeCatch>
<physicalOffset>0x128D000</physicalOffset>
<physicalOffset>0x140D000</physicalOffset>
<physicalRegionSize>0x120000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
Expand All @@ -170,7 +170,7 @@ Layout Description - Used when building an FSP driver
<section>
<description>Hostboot Runtime Services for Sapphire (6MB)</description>
<eyeCatch>HBRT</eyeCatch>
<physicalOffset>0x13AD000</physicalOffset>
<physicalOffset>0x152D000</physicalOffset>
<physicalRegionSize>0x600000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
Expand All @@ -179,7 +179,7 @@ Layout Description - Used when building an FSP driver
<section>
<description>Hostboot Bootloader (28K)</description>
<eyeCatch>HBBL</eyeCatch>
<physicalOffset>0x19AD000</physicalOffset>
<physicalOffset>0x1B2D000</physicalOffset>
<!-- Physical Size includes Header rounded to ECC valid size -->
<!-- Max size of actual HBBL content is 20K and 22.5K with ECC -->
<physicalRegionSize>0x7000</physicalRegionSize>
Expand All @@ -190,23 +190,23 @@ Layout Description - Used when building an FSP driver
<section>
<description>Global Data (36K)</description>
<eyeCatch>GLOBAL</eyeCatch>
<physicalOffset>0x19B4000</physicalOffset>
<physicalOffset>0x1B34000</physicalOffset>
<physicalRegionSize>0x9000</physicalRegionSize>
<side>sideless</side>
<ecc/>
</section>
<section>
<description>Ref Image Ring Overrides (20K)</description>
<eyeCatch>RINGOVD</eyeCatch>
<physicalOffset>0x19BD000</physicalOffset>
<physicalOffset>0x1B3D000</physicalOffset>
<physicalRegionSize>0x5000</physicalRegionSize>
<side>sideless</side>
<ecc/>
</section>
<section>
<description>SecureBoot Key Transition Partition (16K)</description>
<eyeCatch>SBKT</eyeCatch>
<physicalOffset>0x19C2000</physicalOffset>
<physicalOffset>0x1B42000</physicalOffset>
<physicalRegionSize>0x4000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
Expand All @@ -215,7 +215,7 @@ Layout Description - Used when building an FSP driver
<section>
<description>OCC Lid (1.125M)</description>
<eyeCatch>OCC</eyeCatch>
<physicalOffset>0x19C6000</physicalOffset>
<physicalOffset>0x1B46000</physicalOffset>
<physicalRegionSize>0x120000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
Expand All @@ -226,7 +226,7 @@ Layout Description - Used when building an FSP driver
<!-- We need 266KB per module sort, going to support
40 tables by default, plus ECC -->
<eyeCatch>WOFDATA</eyeCatch>
<physicalOffset>0x1AE6000</physicalOffset>
<physicalOffset>0x1C66000</physicalOffset>
<physicalRegionSize>0xC00000</physicalRegionSize>
<side>sideless</side>
<sha512Version/>
Expand All @@ -235,7 +235,7 @@ Layout Description - Used when building an FSP driver
<section>
<description>Memory Data (128K)</description>
<eyeCatch>MEMD</eyeCatch>
<physicalOffset>0x26E6000</physicalOffset>
<physicalOffset>0x2866000</physicalOffset>
<physicalRegionSize>0x20000</physicalRegionSize>
<side>sideless</side>
<sha512Version/>
Expand All @@ -244,7 +244,7 @@ Layout Description - Used when building an FSP driver
<section>
<description>Centaur Hw Ref Image (12K)</description>
<eyeCatch>CENHWIMG</eyeCatch>
<physicalOffset>0x2706000</physicalOffset>
<physicalOffset>0x2886000</physicalOffset>
<physicalRegionSize>0x3000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
Expand All @@ -253,7 +253,7 @@ Layout Description - Used when building an FSP driver
<section>
<description>Secure Boot (144K)</description>
<eyeCatch>SECBOOT</eyeCatch>
<physicalOffset>0x2709000</physicalOffset>
<physicalOffset>0x2889000</physicalOffset>
<physicalRegionSize>0x24000</physicalRegionSize>
<side>sideless</side>
<ecc/>
Expand All @@ -262,7 +262,7 @@ Layout Description - Used when building an FSP driver
<section>
<description>Open CAPI Memory Buffer (OCMB) Firmware (300K)</description>
<eyeCatch>OCMBFW</eyeCatch>
<physicalOffset>0x272D000</physicalOffset>
<physicalOffset>0x28AD000</physicalOffset>
<physicalRegionSize>0x4B000</physicalRegionSize>
<side>sideless</side>
<sha512Version/>
Expand Down
8 changes: 4 additions & 4 deletions src/build/buildpnor/pnorLayoutFake.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2015,2017 -->
<!-- Contributors Listed Below - COPYRIGHT 2015,2019 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
Expand Down Expand Up @@ -128,17 +128,17 @@ Layout Description
</section>
<section>
<!-- NOTE: smaller than official layout for fake-PNOR -->
<description>Hostboot Extended image (4.96MB)</description>
<description>Hostboot Extended image (6.46MB)</description>
<eyeCatch>HBI</eyeCatch>
<physicalOffset>0x10A000</physicalOffset>
<physicalRegionSize>0x4F6000</physicalRegionSize>
<physicalRegionSize>0x676000</physicalRegionSize>
<side>sideless</side>
</section>
<section>
<!-- NOTE: smaller than official layout for fake-PNOR -->
<description>Centaur Hw Image (12K)</description>
<eyeCatch>CENHWIMG</eyeCatch>
<physicalOffset>0x600000</physicalOffset>
<physicalOffset>0x780000</physicalOffset>
<physicalRegionSize>0x3000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
Expand Down

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