chore(ssa refactor) : Research on region labelling [DO NOT MERGE]

[kevaundray]

Description

In this PR I was attempting to add region labelling to the ACIR code, which would allow us to print the GeneratedACIR and it will tell us what SSA instruction created it.

The main problem seems to be that opcodes are laid down lazilly so an add instruction won't necessarilly create an ACIR opcode. See #1427 for more detail.

Here is an example program:

fn main(x : Field, y : pub Field) -> pub Field {
    let z = x + x;
    let t = z - y;
    z / t
}

The code will output:

region start: Binary(Binary { lhs: Id(0), rhs: Id(0), operator: Add })
region start: Binary(Binary { lhs: Id(2), rhs: Id(1), operator: Sub })
region start: Binary(Binary { lhs: Id(2), rhs: Id(3), operator: Div })
OPCODE : EXPR [ (2, _1) (-1, _2) (-1, _3) 0 ]
region end: Binary(Binary { lhs: Id(0), rhs: Id(0), operator: Add })
region end: Binary(Binary { lhs: Id(2), rhs: Id(1), operator: Sub })
OPCODE : DIR::INVERT (_3, out: _4) 
OPCODE : EXPR [ (2, _1) (-1, _2) (-1, _5) 0 ]
OPCODE : EXPR [ (1, _4, _5) -1 ]
OPCODE : EXPR [ (2, _1) (-1, _6) 0 ]
OPCODE : EXPR [ (1, _4, _6) (-1, _7) 0 ]
region end: Binary(Binary { lhs: Id(2), rhs: Id(3), operator: Div })

You can ignore the fact that we are not printing the ssa IR instructions properly. Due to not every SSA IR instruction mapping to an opcode, the region start of each instruction is grouped together unfortunately.

The region_end lines map more closely to what is actually happening, ie:

OPCODE : EXPR [ (2, _1) (-1, _2) (-1, _3) 0 ]
region end: Binary(Binary { lhs: Id(0), rhs: Id(0), operator: Add })
region end: Binary(Binary { lhs: Id(2), rhs: Id(1), operator: Sub })

This is the region for add and sub, two ssa ir instructions produced one ACIR opcode.

OPCODE : DIR::INVERT (_3, out: _4) 
OPCODE : EXPR [ (2, _1) (-1, _2) (-1, _5) 0 ]
OPCODE : EXPR [ (1, _4, _5) -1 ]
OPCODE : EXPR [ (2, _1) (-1, _6) 0 ]
OPCODE : EXPR [ (1, _4, _6) (-1, _7) 0 ]
region end: Binary(Binary { lhs: Id(2), rhs: Id(3), operator: Div })

This is the region for div, one ssa div instruction produced five acir opcodes

[TomAFrench]

Closing as we have debug info added in #1864