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fix: Switch Brillig Store and Load index to RegisterMemIndex #193
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guipublic
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Apr 11, 2023
kevaundray
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May 23, 2023
#152) * cargo.toml * add initial code for non deterministic vm * fix clippy * remove unary op -- can be simulated with binary op * refactor API: - use ValueKind - refactor opcodes needed * re-export brillig bytecode * add brillig * brillig is now re-exported from acir * use acir_field instead of acir * wip * add directive todo * feat: Add serialization for brillig bytecode (#158) * add serialization for brillig * cargo fmt * feat: Solve Brillig Directive (#159) * solve the brillig directive * move brilling_bytecode out of acvm * go back to correct process_opcodes * cargo fmt * switch to using insert_witness method * RegisterIndex -> RegisterMemIndex * - use `Label` - RegisterIndex -> RegisterMemIndex * export RegisterMemIndex * conversion func for registerIndex * add jmpifnot * feat: Add trap opcode (#161) * trap opcode in Opcode enum * process trap opcode * feat: Brillig JMP and JMPIF (#162) * brillig jmp process_opcode * making jump test * starting jmp opcode test * test brillig jumps * debug cleanup * remove comments from Value in vm * fix to stop VM on Trap opcode (#163) * feat: JMPIFNOT (#165) * jmp if not opcode and test * jmp if not opode and test * fix jmpifnot test * carog fmt * remove unnecessary registers in jmpif test * cargo fmt * feat: Mov Opcode in Brillig (#166) * MOV opcode in brillig and a basic test * cargo fmt * fixed move to not only move source into dest, not a full swap * cargo fmt * feat: Comparison Binary Ops (#167) * add lt and lte comparisons to BinaryOp + tests * briefly delete test * cargo fmt * temp remove test * move Brillig from being a directive to an Opcode (#169) * bootstrap register allocation * add bootstrap hack * increment program counter * feat: Brillig oracle opcode (#170) * Brillig OracleWait and test for it * cleanup and add stalled brillig data to unresolved_opcodes * wip --------- Co-authored-by: Kevaundray Wedderburn <[email protected]> * feat: Reduce brillig bytecodes sent to VM after oracle wait (#173) * VM returns a program counter to enable the caller to restart execution at where the oracle was waiting * fix inputs for brillig oracle * remove comment * feat: Brillig Stop opcode (#174) * stop opcode * stop opcode * feat: Brillig Call Opcode (#175) * brillig call opcode * jump from register * add expect instead of unwrap for register into label * feat: Brillig Oracle Predicate (#176) * brillig oracle predicate * switch predicate from brillig oracle to brillig itself * fix brillig predicate write * feat: Brillig Memory (#178) * initial brillig vm memory * some more fixup with handling array outputs from vm * load opcode test * load and store tests * remove arrayid value type * move to BTreeMap for array heap * rename brillig inputs and outputs * switch store load index field to RegisterMemIndex (#193) * return whole unresolved brillig opcode instead of just the oracle for the caller to access * feat: Brillig oracle array outputs (#195) * handle oracle array outputs * switch to single output register * simplify memory opcode creation in oracle arr test * chore(acvm): couple unresolved brillig and brillig oracle to make resolving less brittle * add OracleInput struct and handle them in brillig solver (#199) * fix: Change OracleInput to an enum (#200) * Fix OracleInput representation * Fix tests * feat!: Use OracleOutput enum in OracleData (#201) * make an OracleOutput enum similar to OracleInput * delete unnecessary comments * update array start to registermemindex as it can be a constant (#205) * handle unresolved brillig data when stalled correctly (#208) * feat!: Handle result type of Binary Ops in Brillig (#202) * initial work for wrapping addition with unsigned int * new evaluate method for bin ops that checks the res_type and wraps ops appropriately * handle signed and unsigned division for binary ops * initial call stack opcodes and their impl in VM (#215) * fix reference to old Opcode::Call (#217) * change id_as_value typ for brillig inputs (#222) * bitwise operators, shifts, and cleanup for BinaryOp.evaluate (#224) * move insertion of array input to brillig only if entire array is solved (#226) * small fix for comparison * Return failure on trap (#229) * feat(brillig): experiments * Low level pointer machine * chore: additional testing * chore: additional testing * comment non-working oracle tests * Clippy and test fixes * Rework Brillig oracles, rename ForeignCall * Fix: test reorder issue * cargo format * chore: align tests * added double oracle in one brillig gen * Remove MIN_REGISTER_VALUES * Remove register_allocation_indices hack * cargo fmt * cargo fmt and cargo clippy missing usage of solved_brillig_data * Add Brillig to cspell * Update acir/src/circuit/opcodes.rs * Update acvm/src/compiler/transformers/fallback.rs * Update acvm/src/pwg.rs * Update brillig_bytecode/src/opcodes.rs * Update brillig_bytecode/src/lib.rs * Update brillig_bytecode/src/opcodes.rs * cargo fmt * chore: comment updates * Update brillig_bytecode/src/lib.rs Co-authored-by: Tom French <[email protected]> * rename `Simple` to `Single` and add a comment for Inputs and Outputs * Update acvm/src/pwg.rs * Update brillig_bytecode/src/opcodes.rs * Update brillig_bytecode/src/opcodes.rs * Update brillig_bytecode/src/opcodes.rs * Update brillig_bytecode/src/opcodes.rs * Update brillig_bytecode/src/opcodes.rs * Update brillig_bytecode/src/value.rs * Update brillig_bytecode/src/lib.rs * Update brillig_bytecode/src/lib.rs * Update brillig_bytecode/src/lib.rs * Update brillig_bytecode/src/lib.rs * Update brillig_bytecode/src/value.rs * Update brillig_bytecode/src/registers.rs * Update brillig_bytecode/src/value.rs * Update brillig_bytecode/src/opcodes.rs * Update brillig_bytecode/src/opcodes.rs * Update brillig_bytecode/src/lib.rs * Update brillig_bytecode/src/lib.rs * Update brillig_bytecode/src/lib.rs * Update brillig_bytecode/src/lib.rs * Update acvm/src/pwg.rs * add `RegisterIndex` comment as doc comment * cargo fmt * Update acvm/src/pwg.rs * move brillig constructs into ACIR into its own module -- This will replace directives * modify rest of the codebase to match this * Update brillig_bytecode/src/opcodes.rs * Update brillig_bytecode/src/opcodes.rs * remove unused UnresolvedData struct * chore: move process binary int op to more appropriate part of file * chore: fix comment on wait_for_foreign_call * now waiting * chore: whitespace changes * chore: whitespace changes * Apply suggestions from code review * fix: properly handle `brillig_bytecode` default feature * Update acvm/src/pwg.rs * Apply suggestions from code review * chore: add `brillig_bytecode` to `publish.yml` * chore: make `Value` and `RegisterIndex` fields private (#308) * chore: make fields private on `Value` and `RegisterIndex` * Update brillig_bytecode/src/value.rs --------- Co-authored-by: kevaundray <[email protected]> * Update brillig_bytecode/src/lib.rs Co-authored-by: Tom French <[email protected]> * Update brillig_bytecode/Cargo.toml Co-authored-by: Tom French <[email protected]> * Update acvm/src/pwg.rs Co-authored-by: Tom French <[email protected]> * Update acir/src/circuit/brillig.rs Co-authored-by: Tom French <[email protected]> * rename brillig_bytecode to brillig_vm * change UnresolvedBrillig to UnresolvedBrilligCall * Update brillig_vm/src/value.rs * chore: rename `unresolved_brilligs` to unresolved_brillig_calls --------- Co-authored-by: Maxim Vezenov <[email protected]> Co-authored-by: Joss <[email protected]> Co-authored-by: joss-aztec <[email protected]> Co-authored-by: jfecher <[email protected]> Co-authored-by: guipublic <[email protected]> Co-authored-by: guipublic <[email protected]> Co-authored-by: ludamad <[email protected]> Co-authored-by: ludamad <[email protected]> Co-authored-by: Tom French <[email protected]> Co-authored-by: Tom French <[email protected]>
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cargo fmtwith default settings.Additional context
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