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fix: Change OracleInput to an enum (#200)
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* Fix OracleInput representation

* Fix tests
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jfecher authored Apr 17, 2023
1 parent 27cdadd commit 7ba98fc
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Showing 6 changed files with 506 additions and 509 deletions.
12 changes: 4 additions & 8 deletions acvm/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -490,10 +490,8 @@ mod test {
result: RegisterIndex(3),
};

let invert_oracle_input = OracleInput {
register_mem_index: RegisterMemIndex::Register(RegisterIndex(0)),
length: 0,
};
let invert_oracle_input =
OracleInput::RegisterMemIndex(RegisterMemIndex::Register(RegisterIndex(0)));

let invert_oracle = brillig_bytecode::Opcode::Oracle(brillig_bytecode::OracleData {
name: "invert".into(),
Expand Down Expand Up @@ -617,10 +615,8 @@ mod test {
result: RegisterIndex(3),
};

let invert_oracle_input = OracleInput {
register_mem_index: RegisterMemIndex::Register(RegisterIndex(0)),
length: 0,
};
let invert_oracle_input =
OracleInput::RegisterMemIndex(RegisterMemIndex::Register(RegisterIndex(0)));

let invert_oracle = brillig_bytecode::Opcode::Oracle(brillig_bytecode::OracleData {
name: "invert".into(),
Expand Down
29 changes: 8 additions & 21 deletions acvm/src/pwg/brillig.rs
Original file line number Diff line number Diff line change
@@ -1,9 +1,7 @@
use std::collections::BTreeMap;

use acir::{
brillig_bytecode::{
ArrayHeap, Opcode, OracleData, Registers, Typ, VMOutputState, VMStatus, Value, VM,
},
brillig_bytecode::{ArrayHeap, Opcode, OracleData, Registers, Typ, VMStatus, Value, VM},
circuit::opcodes::{Brillig, BrilligInputs, BrilligOutputs},
native_types::Witness,
FieldElement,
Expand Down Expand Up @@ -112,9 +110,11 @@ impl BrilligSolver {
let input_registers = Registers { inner: input_register_values };
let vm = VM::new(input_registers, input_memory, brillig.bytecode.clone());

let VMOutputState { registers, program_counter, status, memory } = vm.process_opcodes();
let vm_output = vm.process_opcodes();

if vm_output.status == VMStatus::OracleWait {
let program_counter = vm_output.program_counter;

if status == VMStatus::OracleWait {
let current_opcode = &brillig.bytecode[program_counter];
let mut data = match current_opcode.clone() {
Opcode::Oracle(data) => data,
Expand All @@ -126,20 +126,7 @@ impl BrilligSolver {
}
};

let mut input_values = Vec::new();
for oracle_input in data.clone().inputs {
if oracle_input.length == 0 {
let x = registers.get(oracle_input.register_mem_index).inner;
input_values.push(x);
} else {
let array_id = registers.get(oracle_input.register_mem_index);
let array = memory[&array_id].clone();
let heap_fields =
array.memory_map.into_values().map(|value| value.inner).collect::<Vec<_>>();
input_values.extend(heap_fields);
}
}

let input_values = vm_output.map_input_values(&data);
data.input_values = input_values;

return Ok(OpcodeResolution::InProgressBrillig(OracleWaitInfo {
Expand All @@ -148,13 +135,13 @@ impl BrilligSolver {
}));
}

for (output, register_value) in brillig.outputs.iter().zip(registers) {
for (output, register_value) in brillig.outputs.iter().zip(vm_output.registers) {
match output {
BrilligOutputs::Simple(witness) => {
insert_witness(*witness, register_value.inner, initial_witness)?;
}
BrilligOutputs::Array(witness_arr) => {
let array = memory[&register_value].memory_map.values();
let array = vm_output.memory[&register_value].memory_map.values();
for (witness, value) in witness_arr.iter().zip(array) {
insert_witness(*witness, value.inner, initial_witness)?;
}
Expand Down
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