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add tm1829 module to dev branch #984
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This code is taken from the WS2812 module with modified timings and inverted logic levels
usage like ws2812 module
Thanks a lot! I'd like to see two additional things:
@devsaurus in #920 (comment) you mentioned some verification you wanted to perform? |
Can I give this a 👎 or at least a hold. We shouldn't be adding more modules which break the Espressif timing guidelines and cause the CPU to crater, until we agree a policy for addressing these issues. In this case interrupts are disabled for ~40N µSec where N is the number of LEDs. |
Not me. In general verification that the code in |
Copy-and-paste programming, fonctions comments were wrong in ws2812 module, and ... same here :/ It looks like a similar protocol than ws2812, we could try to share code / use similar implementation. |
The main difference is that the logic is inverted that is each data bit is a low-high rather than high-low, so whilst your encoding scheme can easily be mapped onto the 1xxxxxxxx0 bit sequences output by the uart, this will need to be shifted one sub-bit for the TM1289. We could get this to work, I think, but test HW and an oscilloscope will be needed. Or add a logic inverter in the path. |
@h3ndrik do you intend to fix the code based on the the comments here? If not then please close he PR. |
No feedback in more than two weeks -> closing. |
This code is taken from the WS2812 module with modified timings and inverted logic levels
see #920: this is a resubmission after the module cleanup
also add some API description (#774)