Add cRIO FPGA and Hybrid Mode tests (#207)

Add three new system tests for a cRIO 9045 and 3x 9401s: - Hybrid (2 FPGA slots and 1 Scan Mode) - FPGA (2 FPGA slots) - UDV (no C Series IO, only UDVs of various datatypes)
ni · Jun 23, 2022 · 8dad96f · 8dad96f
1 parent aa58a96
commit 8dad96f
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Showing 24 changed files with 94,061 additions and 1 deletion.
diff --git a/Custom Device Source/Scan Engine.lvproj b/Custom Device Source/Scan Engine.lvproj
@@ -1,4 +1,4 @@
-<?xml version='1.0' encoding='UTF-8'?>
+<?xml version='1.0' encoding='UTF-8'?>
 <Project Type="Project" LVVersion="19008000">
 	<Property Name="CCSymbols" Type="Str">Debugging,False;</Property>
 	<Property Name="NI.LV.All.SourceOnly" Type="Bool">true</Property>
@@ -64,6 +64,9 @@
 					</Item>
 					<Item Name="Scan Engine Specialty Digital System Tests.lvclass" Type="LVClass" URL="../Tests/Specialty Digital System Tests/Scan Engine Specialty Digital System Tests.lvclass"/>
 				</Item>
+				<Item Name="cRIO" Type="Folder">
+					<Item Name="cRIO System Tests.lvclass" Type="LVClass" URL="../Tests/cRIO System Tests/cRIO System Tests.lvclass"/>
+				</Item>
 			</Item>
 			<Item Name="Unit" Type="Folder">
 				<Item Name="Scripting API" Type="Folder">
@@ -669,6 +672,11 @@
 				<Item Name="Registry RtKey.ctl" Type="VI" URL="/&lt;vilib&gt;/registry/registry.llb/Registry RtKey.ctl"/>
 				<Item Name="Registry SAM.ctl" Type="VI" URL="/&lt;vilib&gt;/registry/registry.llb/Registry SAM.ctl"/>
 				<Item Name="Open Registry Key.vi" Type="VI" URL="/&lt;vilib&gt;/registry/registry.llb/Open Registry Key.vi"/>
+				<Item Name="sub_Random U32.vi" Type="VI" URL="/&lt;vilib&gt;/numeric/sub_Random U32.vi"/>
+				<Item Name="Random Number (Range) U64.vi" Type="VI" URL="/&lt;vilib&gt;/numeric/Random Number (Range) U64.vi"/>
+				<Item Name="Random Number (Range) I64.vi" Type="VI" URL="/&lt;vilib&gt;/numeric/Random Number (Range) I64.vi"/>
+				<Item Name="Random Number (Range) DBL.vi" Type="VI" URL="/&lt;vilib&gt;/numeric/Random Number (Range) DBL.vi"/>
+				<Item Name="Random Number (Range).vi" Type="VI" URL="/&lt;vilib&gt;/numeric/Random Number (Range).vi"/>
 			</Item>
 			<Item Name="user.lib" Type="Folder">
 				<Item Name="Current VIs Parents Ref__ogtk.vi" Type="VI" URL="/&lt;userlib&gt;/_OpenG.lib/appcontrol/appcontrol.llb/Current VIs Parents Ref__ogtk.vi"/>

diff --git a/Custom Device Source/Tests/cRIO System Tests/Assets/cRIO 9045 FPGA Project/FPGA Main.vi b/Custom Device Source/Tests/cRIO System Tests/Assets/cRIO 9045 FPGA Project/FPGA Main.vi
diff --git a/...Source/Tests/cRIO System Tests/Assets/cRIO 9045 FPGA Project/VS Eco cRIO 9045 FPGA.lvproj b/...Source/Tests/cRIO System Tests/Assets/cRIO 9045 FPGA Project/VS Eco cRIO 9045 FPGA.lvproj