Performance issues when using multiple PWM In channels

[JWA74]

Describe the bug
We have seen performance issues when using the FPGA addon, when using multiple PWM In channels (or to be exact “Digital PWM Measurement” part of the NI VeriStand FPGA Add-on Specialty I/O).
We have created a FPGA bitfile that allows the customer to read 128 Digital Static Measurement channels as well as 128 Digital PWM Measurement channels so a decent number of controls / indicators on the FPGA.

Steps to reproduce the behavior:

1. Create a FPGA that makes use of all digital channels on a PXIe-7820, make use of the NI VeriStand FPGA Add-on Specialty I/O functions so the user gets both Digital Static Measurement and Digital PWM Measurement on all 128 channels.
2. Import the bitfile in FPGA Add-on Custom Device, import all DI channels (128) and then import a subset of the DI-PWM channels, let us say 30. Deploy and check the HP count, you will see that we start having issues keeping up. Add another 10 (40 in total), and you will see the HP count increasing resulting in that the actual loop-rate is reduced from the desired 1000Hz.
3. Calculation done on the RT side (included in the FPGA Add-on Custom device) should be easy from the FPGA cluster read, why do we see such a performance hit when adding 30 or so Digital PWM Measurement channels?

Please complete the following information:

• OS: NI Linux RTOS 23.5 Image
• NI VeriStand 2021