v0.8.4+luau616

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "luau0-src"
-version = "0.8.3+luau614"
+version = "0.8.4+luau616"
 authors = ["Aleksandr Orlenko <[email protected]>"]
 edition = "2021"
 repository = "https://github.com/khvzak/luau-src-rs"

luau/CodeGen/include/Luau/IrData.h

@@ -398,6 +398,7 @@ enum class IrCmd : uint8_t
     // A, B: tag
     // C: block/vmexit/undef
     // In final x64 lowering, A can also be Rn
+    // When DebugLuauAbortingChecks flag is enabled, A can also be Rn
     // When undef is specified instead of a block, execution is aborted on check failure
     CHECK_TAG,
 

luau/CodeGen/include/Luau/IrVisitUseDef.h

@@ -4,6 +4,8 @@
 #include "Luau/Common.h"
 #include "Luau/IrData.h"
 
+LUAU_FASTFLAG(LuauCodegenRemoveDeadStores2)
+
 namespace Luau
 {
 namespace CodeGen
@@ -186,7 +188,15 @@ static void visitVmRegDefsUses(T& visitor, IrFunction& function, const IrInst& i
         visitor.def(inst.b);
         break;
     case IrCmd::FALLBACK_FORGPREP:
-        visitor.use(inst.b);
+        if (FFlag::LuauCodegenRemoveDeadStores2)
+        {
+            // This instruction doesn't always redefine Rn, Rn+1, Rn+2, so we have to mark it as implicit use
+            visitor.useRange(vmRegOp(inst.b), 3);
+        }
+        else
+        {
+            visitor.use(inst.b);
+        }
 
         visitor.defRange(vmRegOp(inst.b), 3);
         break;
@@ -204,6 +214,11 @@ static void visitVmRegDefsUses(T& visitor, IrFunction& function, const IrInst& i
         visitor.use(inst.a);
         break;
 
+        // After optimizations with DebugLuauAbortingChecks enabled, CHECK_TAG Rn, tag, block instructions are generated
+    case IrCmd::CHECK_TAG:
+        visitor.maybeUse(inst.a);
+        break;
+
     default:
         // All instructions which reference registers have to be handled explicitly
         CODEGEN_ASSERT(inst.a.kind != IrOpKind::VmReg);

luau/CodeGen/include/Luau/OptimizeDeadStore.h

@@ -0,0 +1,16 @@
+// This file is part of the Luau programming language and is licensed under MIT License; see LICENSE.txt for details
+#pragma once
+
+#include "Luau/IrData.h"
+
+namespace Luau
+{
+namespace CodeGen
+{
+
+struct IrBuilder;
+
+void markDeadStoresInBlockChains(IrBuilder& build);
+
+} // namespace CodeGen
+} // namespace Luau

luau/CodeGen/src/AssemblyBuilderX64.cpp

@@ -6,8 +6,6 @@
 #include <stdarg.h>
 #include <stdio.h>
 
-LUAU_FASTFLAGVARIABLE(LuauCache32BitAsmConsts, false)
-
 namespace Luau
 {
 namespace CodeGen
@@ -1041,33 +1039,24 @@ OperandX64 AssemblyBuilderX64::i64(int64_t value)
 
 OperandX64 AssemblyBuilderX64::f32(float value)
 {
-    if (FFlag::LuauCache32BitAsmConsts)
-    {
-        uint32_t as32BitKey;
-        static_assert(sizeof(as32BitKey) == sizeof(value), "Expecting float to be 32-bit");
-        memcpy(&as32BitKey, &value, sizeof(value));
+    uint32_t as32BitKey;
+    static_assert(sizeof(as32BitKey) == sizeof(value), "Expecting float to be 32-bit");
+    memcpy(&as32BitKey, &value, sizeof(value));
 
-        if (as32BitKey != ~0u)
-        {
-            if (int32_t* prev = constCache32.find(as32BitKey))
-                return OperandX64(SizeX64::dword, noreg, 1, rip, *prev);
-        }
+    if (as32BitKey != ~0u)
+    {
+        if (int32_t* prev = constCache32.find(as32BitKey))
+            return OperandX64(SizeX64::dword, noreg, 1, rip, *prev);
+    }
 
-        size_t pos = allocateData(4, 4);
-        writef32(&data[pos], value);
-        int32_t offset = int32_t(pos - data.size());
+    size_t pos = allocateData(4, 4);
+    writef32(&data[pos], value);
+    int32_t offset = int32_t(pos - data.size());
 
-        if (as32BitKey != ~0u)
-            constCache32[as32BitKey] = offset;
+    if (as32BitKey != ~0u)
+        constCache32[as32BitKey] = offset;
 
-        return OperandX64(SizeX64::dword, noreg, 1, rip, offset);
-    }
-    else
-    {
-        size_t pos = allocateData(4, 4);
-        writef32(&data[pos], value);
-        return OperandX64(SizeX64::dword, noreg, 1, rip, int32_t(pos - data.size()));
-    }
+    return OperandX64(SizeX64::dword, noreg, 1, rip, offset);
 }
 
 OperandX64 AssemblyBuilderX64::f64(double value)

luau/CodeGen/src/CodeAllocator.cpp

@@ -27,6 +27,10 @@ const size_t kPageSize = sysconf(_SC_PAGESIZE);
 #endif
 #endif
 
+#ifdef __APPLE__
+extern "C" void sys_icache_invalidate(void* start, size_t len);
+#endif
+
 static size_t alignToPageSize(size_t size)
 {
     return (size + kPageSize - 1) & ~(kPageSize - 1);
@@ -98,7 +102,11 @@ static void makePagesExecutable(uint8_t* mem, size_t size)
 
 static void flushInstructionCache(uint8_t* mem, size_t size)
 {
+#ifdef __APPLE__
+    sys_icache_invalidate(mem, size);
+#else
     __builtin___clear_cache((char*)mem, (char*)mem + size);
+#endif
 }
 #endif
 

luau/CodeGen/src/CodeGenLower.h

@@ -8,6 +8,7 @@
 #include "Luau/IrDump.h"
 #include "Luau/IrUtils.h"
 #include "Luau/OptimizeConstProp.h"
+#include "Luau/OptimizeDeadStore.h"
 #include "Luau/OptimizeFinalX64.h"
 
 #include "EmitCommon.h"
@@ -26,6 +27,7 @@ LUAU_FASTFLAG(DebugCodegenSkipNumbering)
 LUAU_FASTINT(CodegenHeuristicsInstructionLimit)
 LUAU_FASTINT(CodegenHeuristicsBlockLimit)
 LUAU_FASTINT(CodegenHeuristicsBlockInstructionLimit)
+LUAU_FASTFLAG(LuauCodegenRemoveDeadStores2)
 
 namespace Luau
 {
@@ -309,6 +311,9 @@ inline bool lowerFunction(IrBuilder& ir, AssemblyBuilder& build, ModuleHelpers&
                 stats->blockLinearizationStats.constPropInstructionCount += constPropInstructionCount;
             }
         }
+
+        if (FFlag::LuauCodegenRemoveDeadStores2)
+            markDeadStoresInBlockChains(ir);
     }
 
     std::vector<uint32_t> sortedBlocks = getSortedBlockOrder(ir.function);

luau/CodeGen/src/IrLoweringA64.cpp

@@ -11,10 +11,9 @@
 #include "lstate.h"
 #include "lgc.h"
 
-LUAU_DYNAMIC_FASTFLAGVARIABLE(LuauCodeGenFixBufferLenCheckA64, false)
 LUAU_FASTFLAGVARIABLE(LuauCodeGenVectorA64, false)
 
-LUAU_FASTFLAG(LuauCodegenVectorTag)
+LUAU_FASTFLAG(LuauCodegenVectorTag2)
 
 namespace Luau
 {
@@ -680,7 +679,7 @@ void IrLoweringA64::lowerInst(IrInst& inst, uint32_t index, const IrBlock& next)
         {
             build.fadd(inst.regA64, regOp(inst.a), regOp(inst.b));
 
-            if (!FFlag::LuauCodegenVectorTag)
+            if (!FFlag::LuauCodegenVectorTag2)
             {
                 RegisterA64 tempw = regs.allocTemp(KindA64::w);
                 build.mov(tempw, LUA_TVECTOR);
@@ -710,7 +709,7 @@ void IrLoweringA64::lowerInst(IrInst& inst, uint32_t index, const IrBlock& next)
         {
             build.fsub(inst.regA64, regOp(inst.a), regOp(inst.b));
 
-            if (!FFlag::LuauCodegenVectorTag)
+            if (!FFlag::LuauCodegenVectorTag2)
             {
                 RegisterA64 tempw = regs.allocTemp(KindA64::w);
                 build.mov(tempw, LUA_TVECTOR);
@@ -740,7 +739,7 @@ void IrLoweringA64::lowerInst(IrInst& inst, uint32_t index, const IrBlock& next)
         {
             build.fmul(inst.regA64, regOp(inst.a), regOp(inst.b));
 
-            if (!FFlag::LuauCodegenVectorTag)
+            if (!FFlag::LuauCodegenVectorTag2)
             {
                 RegisterA64 tempw = regs.allocTemp(KindA64::w);
                 build.mov(tempw, LUA_TVECTOR);
@@ -770,7 +769,7 @@ void IrLoweringA64::lowerInst(IrInst& inst, uint32_t index, const IrBlock& next)
         {
             build.fdiv(inst.regA64, regOp(inst.a), regOp(inst.b));
 
-            if (!FFlag::LuauCodegenVectorTag)
+            if (!FFlag::LuauCodegenVectorTag2)
             {
                 RegisterA64 tempw = regs.allocTemp(KindA64::w);
                 build.mov(tempw, LUA_TVECTOR);
@@ -800,7 +799,7 @@ void IrLoweringA64::lowerInst(IrInst& inst, uint32_t index, const IrBlock& next)
         {
             build.fneg(inst.regA64, regOp(inst.a));
 
-            if (!FFlag::LuauCodegenVectorTag)
+            if (!FFlag::LuauCodegenVectorTag2)
             {
                 RegisterA64 tempw = regs.allocTemp(KindA64::w);
                 build.mov(tempw, LUA_TVECTOR);
@@ -1184,7 +1183,7 @@ void IrLoweringA64::lowerInst(IrInst& inst, uint32_t index, const IrBlock& next)
         build.fcvt(temps, tempd);
         build.dup_4s(inst.regA64, castReg(KindA64::q, temps), 0);
 
-        if (!FFlag::LuauCodegenVectorTag)
+        if (!FFlag::LuauCodegenVectorTag2)
         {
             build.mov(tempw, LUA_TVECTOR);
             build.ins_4s(inst.regA64, tempw, 3);
@@ -1629,11 +1628,7 @@ void IrLoweringA64::lowerInst(IrInst& inst, uint32_t index, const IrBlock& next)
                 RegisterA64 tempx = castReg(KindA64::x, temp);
                 build.sub(tempx, tempx, regOp(inst.b)); // implicit uxtw
                 build.cmp(tempx, uint16_t(accessSize));
-
-                if (DFFlag::LuauCodeGenFixBufferLenCheckA64)
-                    build.b(ConditionA64::Less, target); // note: this is a signed 64-bit comparison so that out of bounds offset fails
-                else
-                    build.b(ConditionA64::LessEqual, target); // note: this is a signed 64-bit comparison so that out of bounds offset fails
+                build.b(ConditionA64::Less, target); // note: this is a signed 64-bit comparison so that out of bounds offset fails
             }
         }
         else if (inst.b.kind == IrOpKind::Constant)