-
Notifications
You must be signed in to change notification settings - Fork 1.5k
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
<vector>
: Add ASan annotations.
#2071
Conversation
Co-authored-by: Michael Schellenberger Costa <[email protected]>
Co-authored-by: Michael Schellenberger Costa <[email protected]>
This comment has been minimized.
This comment has been minimized.
This comment has been minimized.
This comment has been minimized.
This comment has been minimized.
This comment has been minimized.
This comment has been minimized.
This comment has been minimized.
FYI, internal MSVC-PR-356165 needs to be merged before this can be merged internally. |
Co-authored-by: Michael Schellenberger Costa <[email protected]>
This comment has been minimized.
This comment has been minimized.
✔️ MSVC-PR mirroring note:As this PR adds new source files and a new lib, we'll need to update setup - done in MSVC-PR-368993. |
#pragma comment(linker, \ | ||
"/alternatename:___sanitizer_annotate_contiguous_container=___sanitizer_annotate_contiguous_container_default") | ||
#pragma comment(linker, "/alternatename:__Asan_vector_should_annotate=__Asan_vector_should_annotate_default") | ||
#elif defined(_M_X64) || defined(_M_ARM) || defined(_M_ARM64) |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
I observe that there may be interesting ARM64EC (or CHPE) interactions with name mangling, but I can't point to specific issues, so no change requested.
Thanks for this major improvement to the STL's most important data structure! 🚀 ✔️ 🎉 😻 |
Good luck with string! |
Add ASan container annotations to vector. This should allow ASan to catch additional errors when using vector.
Specifically this will catch accesses from [
v.data() + v.size()
,v.data() + v.capacity()
) which would otherwise be missed as they are legal memory addresses.Closes #2030