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1. cva6 cva6 Public

   Forked from 10x-Engineers/cva6

   The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

   SystemVerilog

2. FIFO_Memory FIFO_Memory Public

   FIFO Memory Unit

   Verilog

3. OpenROAD-flow-scripts OpenROAD-flow-scripts Public

   Forked from The-OpenROAD-Project/OpenROAD-flow-scripts

   OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

   Verilog

4. Single_Cycle_RISC-V_Processor_core Single_Cycle_RISC-V_Processor_core Public

   Single Cycle RISC-V Processor Core with I-R-B-S-J-U Instruction Formats

   C++

5. UART_Systemverilog UART_Systemverilog Public

   SystemVerilog

6. 10x-Engineers/Infinite-ISP_ReferenceModel 10x-Engineers/Infinite-ISP_ReferenceModel Public

   A Python based fixed-point implementation of the Infinite-ISP design for ASIC and FPGA design and verification.

   Python 19 10