Clear and Set Power Enable bit in Stop mode

mcci-catena · Apr 1, 2019 · 9378cb1 · 9378cb1
1 parent b143625
commit 9378cb1
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Showing 4 changed files with 43 additions and 19 deletions.
diff --git a/src/lib/stm32/Catena_Mx25v8035f.cpp b/src/lib/stm32/Catena_Mx25v8035f.cpp
@@ -1,4 +1,4 @@
-/* Catena_Mx25v8035f.cpp	Fri Dec 01 2017 13:56:52 chwon */
+/* Catena_Mx25v8035f.cpp	Wed Mar 27 2019 11:07:13 chwon */
 
 /*
 
@@ -8,10 +8,10 @@ Module:  Catena_Mx25v8035f.cpp
 	Class for Catena_Mx25v8035f.
 
 Version:
-	V0.6.0	Fri Dec 01 2017 13:56:52 chwon	Edit level 2
+	V0.14.0	Wed Mar 27 2019 11:07:13 chwon	Edit level 3
 
 Copyright notice:
-	This file copyright (C) 2017 by
+	This file copyright (C) 2017, 2019 by
 
 		MCCI Corporation
 		3520 Krums Corners Road
@@ -32,6 +32,9 @@ Revision history:
    0.6.0  Fri Dec 01 2017 13:56:52  chwon
 	Add debug message and fix reading status register.
 
+   0.14.0  Wed Mar 27 2019 11:07:13  chwon
+	Make CS pin to input when power down.
+
 */
 
 #ifdef ARDUINO_ARCH_STM32
@@ -180,6 +183,9 @@ void Catena_Mx25v8035f::end(
 	)
 	{
 	this->m_pSpi->endTransaction(this->m_CS);
+
+	pinMode(this->m_CS, INPUT);
+	digitalWrite(this->m_CS, 0);
 	}
 
 /*
@@ -642,12 +648,24 @@ void Catena_Mx25v8035f::powerDown(
 	SPIClass * const pSpi = this->m_pSpi;
 	uint32_t uSec;
 
+	if (this->m_PowerDown)
+		{
+		digitalWrite(this->m_CS, 1);
+		pinMode(this->m_CS, OUTPUT);
+
+		uSec = micros();
+		while ((micros() - uSec) < 10);
+		}
+
 	pSpi->transfer(this->m_CS, MX25V8035F_CMD_DP);
 
 	/* tDP == Max 10us */
 	uSec = micros();
 	this->m_PowerDown = true;
 	while ((micros() - uSec) < 10);
+
+	pinMode(this->m_CS, INPUT);
+	digitalWrite(this->m_CS, 0);
 	}
 
 /*
@@ -679,6 +697,7 @@ void Catena_Mx25v8035f::powerUp(
 		{
 		uint32_t uSec;
 
+		pinMode(this->m_CS, OUTPUT);
 		digitalWrite(this->m_CS, 0);
 
 		/* tCRDP == Min 20ns */

diff --git a/src/lib/stm32/stm32l0/CatenaStm32L0Rtc.cpp b/src/lib/stm32/stm32l0/CatenaStm32L0Rtc.cpp
@@ -11,7 +11,7 @@ Module:  CatenaStm32L0Rtc.cpp
 	V0.8.0	Fri Mar 08 2019 18:40:03 dhineshkumar	Edit level 5
 
 Copyright notice:
-	This file copyright (C) 2017 by
+	This file copyright (C) 2017-2019 by
 
 		MCCI Corporation
 		3520 Krums Corners Road

diff --git a/src/lib/stm32/stm32l0/CatenaStm32L0_ReadAnalog.cpp b/src/lib/stm32/stm32l0/CatenaStm32L0_ReadAnalog.cpp
@@ -1,4 +1,4 @@
-/* CatenaStm32L0_ReadAnalog.cpp	Mon Feb 18 2019 09:56:32 chwon */
+/* CatenaStm32L0_ReadAnalog.cpp	Wed Mar 27 2019 11:06:04 chwon */
 
 /*
 
@@ -8,7 +8,7 @@ Module:  CatenaStm32L0_ReadAnalog.cpp
 	CatenaStm32L0::ReadAnalog()
 
 Version:
-	V0.14.0	Mon Feb 18 2019 09:56:32 chwon	Edit level 2
+	V0.14.0	Wed Mar 27 2019 11:06:04 chwon	Edit level 3
 
 Copyright notice:
 	This file copyright (C) 2018-2019 by
@@ -32,6 +32,9 @@ Revision history:
    0.14.0  Mon Feb 18 2019 09:56:32  chwon
 	Turn on and off HSI clock if system clock use MSI clock.
 
+   0.14.0  Wed Mar 27 2019 11:06:04  chwon
+	Use HAL_RCC_GetHCLKFreq() instead of CATENA_CFG_SYSCLK.
+
 */
 
 #ifdef ARDUINO_ARCH_STM32
@@ -116,17 +119,18 @@ bool McciCatena::CatenaStm32L0_ReadAnalog(
 	/* make sure that the RCC is generating the low-frequency clock */
 	__HAL_RCC_ADC1_CLK_ENABLE();
 
-#if CATENA_CFG_SYSCLK < 16
-	/* Set the Low Frequency Mode */
-	/* ADC->CCR = ADC_CCR_LFMEN; -- it's not working with MSI clock */
-
-	/* ADC requires HSI clock, so enable it now */
-	LL_RCC_HSI_Enable();
-	while (LL_RCC_HSI_IsReady() != 1U)
+	if (HAL_RCC_GetHCLKFreq() < 16000000)
 		{
-		/* Wait for HSI ready */
+		/* Set the Low Frequency Mode */
+		/* ADC->CCR = ADC_CCR_LFMEN; -- it's not working with MSI clock */
+
+		/* ADC requires HSI clock, so enable it now */
+		LL_RCC_HSI_Enable();
+		while (LL_RCC_HSI_IsReady() != 1U)
+			{
+			/* Wait for HSI ready */
+			}
 		}
-#endif
 
 	fStatusOk = true;
 
@@ -194,9 +198,10 @@ bool McciCatena::CatenaStm32L0_ReadAnalog(
 	ADC1->CR &= ~ADC_CR_ADVREGEN;
 	ADC->CCR &= ~ADC_CCR_VREFEN;
 
-#if CATENA_CFG_SYSCLK < 16
-	LL_RCC_HSI_Disable();
-#endif
+	if (HAL_RCC_GetHCLKFreq() < 16000000)
+		{
+		LL_RCC_HSI_Disable();
+		}
 
 	__HAL_RCC_ADC1_FORCE_RESET();
 	__HAL_RCC_ADC1_RELEASE_RESET();

diff --git a/src/lib/stm32/stm32l0/CatenaStm32L0_Sleep.cpp b/src/lib/stm32/stm32l0/CatenaStm32L0_Sleep.cpp
@@ -11,7 +11,7 @@ Module:  CatenaStm32L0_Sleep.cpp
 	V0.11.1	Fri Mar 08 2019 18:05:26 dhineshkumar	Edit level 2
 
 Copyright notice:
-	This file copyright (C) 2018 by
+	This file copyright (C) 2018-2019 by
 
 		MCCI Corporation
 		3520 Krums Corners Road