[sival/hmac] Add Hmac error conditions Test

Signed-off-by: Ramesh Prakash <[email protected]> Add HMAC error condition test as per chip_hmac_testplan.hjson Incorporated feedback from PR (cherry picked from commit 7802064)
matutem · Feb 4, 2025 · 4a3bcec · 4a3bcec
1 parent 3755e2e
commit 4a3bcec
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diff --git a/hw/top_earlgrey/data/ip/chip_hmac_testplan.hjson b/hw/top_earlgrey/data/ip/chip_hmac_testplan.hjson
@@ -192,13 +192,14 @@
             - `SwUpdateSecretKeyInProcess`: Update secret key when hash is in progress.
             - `SwHashStartWhenActive`: Issue hash start when hash is in progress.
             - `SwPushMsgWhenDisallowed`: Push message when HMAC is not idle.
+	    - `SwInvalidConfig`: Issue when HMAC configured with incorrect digest-size or key-length
             '''
       features: []
       stage: V3
       si_stage: SV3
       lc_states: ["PROD"]
       tests: []
-      bazel: []
+      bazel: ["//sw/device/tests:hmac_error_conditions_test"]
     }
   ]
 }
diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD
@@ -7285,3 +7285,27 @@ opentitan_test(
         "//sw/device/lib/testing/test_framework:ottf_utils",
     ],
 )
+
+opentitan_test(
+    name = "hmac_error_conditions_test",
+    srcs = ["hmac_error_conditions_test.c"],
+    exec_env = dicts.add(
+        EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
+        {
+            "//hw/top_earlgrey:sim_verilator": None,
+            "//hw/top_earlgrey:fpga_cw340_sival": None,
+        },
+    ),
+    verilator = verilator_params(
+        timeout = "long",
+    ),
+    deps = [
+        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//sw/device/lib/arch:device",
+        "//sw/device/lib/base:mmio",
+        "//sw/device/lib/dif:hmac",
+        "//sw/device/lib/runtime:log",
+        "//sw/device/lib/testing:hmac_testutils",
+        "//sw/device/lib/testing/test_framework:ottf_main",
+    ],
+)