Pcells Code Improvement #27
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General Purpose Pcells: PcViaStack PcGRing
Fix Bug in calculation of licon size. round() replacing int() for delta and grid_delta calculation
Nwell blanket added for N-tap parameter option, as it'll be used in pmos18
Files replaced by PcViaStack.py
layout, cell class objects from other pcell classes can be used as arguments. no dependency on main. Avoid 'NoneType with no attribute ...' failures.
cell transformation build in methods are not used. it adds to the complexity of cells, and demands temporary static cells creation.
periphery.rst https://github.com/google/skywater-pdk/blob/main/docs/rules/periphery-rules.rst: Diff and tap are not allowed to extend beyond their abutting edge for N+/P+ Tap Diff removed.
periphery.rst https://github.com/google/skywater-pdk/blob/main/docs/rules/periphery-rules.rst: Diff and tap are not allowed to extend beyond their abutting edge for N+/P+ Tap, Diff removed.
Avoiding "Ambiguous overload variants - multiple method declaration match arguments in Trans.new in PcellDeclaration.procedure"
PcNmos18(width,length,gate_contact.gate_contact_num,lmcon,rmcon,bmcon,tmcon) calls hierarchical finger method _NMOS18FINGER; base transistor cell
eval() be a target of malicious activity. Mos18Finger() updated accordingly.
PcGRing(...,Lmcon,Rmcon,Bmcon,Tmcon) Updated automatically reflected in pcNmos18
Updates of nmos18: 26.08.22 -- sab param, adpatation of pcViaStack fn tran param (to stay in micrometer world) 27.08.22 -- multi-finger purpose.
- Generalize "well" argument at pcViaStack source/drain contact instatiation. - opt for PcPmos18
PcPmos18(width,length,sab,gate_contact,gate_contact_num,finger_num,subring,lmcon,rmcon,bmcon,tmcon) calls hierarchical finger method _PMOS18FINGER; base transistor cell
Fix rounding error in calculating PathLen variable from _GRing method.
DNW: Isolating Pwell for low noise. HVI: Thick Gate Oxide for 5V MOS regions.
Fix typo error where 'D' in pya.DPath was omitted.
Fix typo error where Top contact param is displayed as Right-CA instead of Top-CA
Fix a bug in PcGring code where DNW is only drawn within and abutting n-tap ring edges..
Fix a wrong implementation of dnwell-nwell enclosures rules :drc_rule:`(nwell.5)` & :drc_rule:`(nwell.6)`
N+Tap: Nwell remains as blanket.
Nmos Device in Deep-Nwell base cell: PcMos5d10Finger model:`sky130_fd_pr__nfet_g5v0d10v5` Cross section:https://github.com/google/skywater-pdk/blob/main/docs/rules/device-details/nfet_g5v0d10v5/index.rst
Description: "SkyWater 130nm 5v TG NMOSg5d10 Pcell"
Gate contact param options: Top, Bottom, Both, Alternate.
Parameter constraints for minimum length, allowed gate contact options.
Gate contact param options: Top, Bottom, Both, Alternate.
remove S/D options; not currently used..
lvtn layer defined to block vt-implants for lvt pmos/nmos devices.
Rename PcNmos18 to pclvtNmos18, and PcPmos18 to PclvtPmos18, as the pcell cross-section resembles ones of low vt devices. see: https://github.com/google/skywater-pdk/blob/main/docs/rules/device-details/nfet_01v8_lvt/index.rst https://github.com/google/skywater-pdk/blob/main/docs/rules/device-details/pfet_01v8_lvt/index.rst
1.8v: Parameter constraints for minimum length, allowed gate contact options. 5.0v: remove imported pcell pcNmos18; no use
Parameter constraints for minimum length, allowed gate contact options.
New parameter introduced for Guard ring contact coverage. covmCON ._GRing(well,hvnwell,nwell_hole,w,.l,h,LmCON,RmCON,BmCON,TmCON,covmCON)
estimated calculation of max allowed coverage param. contacts and vias enclosure values are left for user to select.
Introduction of contact coverage parameters for PclvtNmos18, PclvtPmos18, PcMos18Finger, PcMos5d10Finger, and PcNmos5d10 methods with respective coerce manipulation: _lvtNmos18(w, l, sab,gate_contact, gate_contact_num,finger_num,grCovmCON,sdCovmCON) _lvtPmos18(w, l, sab,gate_contact, gate_contact_num,finger_num,subring,grCovmCON,sdCovmCON) _Nmos5d10(w, l, sab,gate_contact, gate_contact_num,finger_num,grCovmCON,sdCovmCON)
Fix bugs in coerce guard ring contact coverage parameter (%). Affected devices: PcNmos5d10, PclvtPmos18, PclvtNmos18
Parameterize High-Vt N-tip Implant param 'n_tip_implant'
Standard Nmos Device in Deep-Nwell base cell: PcMos18Finger model:'sky130_fd_pr__nfet_01v8` Cross section:https://github.com/google/skywater-pdk/blob/main/docs/rules/device-details/nfet_01v8/index.rst
Standard Pmos Device in Deep-Nwell base cell: PcMos18Finger model:`sky130_fd_pr__pfet_01v8` Cross section: https://github.com/google/skywater-pdk/blob/main/docs/rules/device-details/pfet_01v8/index.rst
Fix bugs in contact spacing variable rect_spc. Affected devices: PcNmos5d10, PclvtNmos18, PcNmos18
High-Vt Pmos Device in Nwell base cell: PcMos18Finger model:`sky130_fd_pr__pfet_01v8_hvt` Cross-section: https://github.com/google/skywater-pdk/blob/main/docs/rules/device-details/pfet_01v8_hvt/index.rst
Define Low-Vt identifier areaid.lvt layer GDS:81/108. source: https://github.com/google/skywater-pdk/blob/main/docs/rules/gds_layers.csv
areaid.lvt layer GDS 81/108 marked LVMOS Affected devices: PclvtNmos18, PclvtPmos18.
Change type prefix to 01v8_lvt to match low-vt MOS18 model name
3.3v Nmos native Device in Deep-Nwell base cell: PcMos18Finger model:`sky130_fd_pr__nfet_03v3_nvt` Cross-section: https://github.com/google/skywater-pdk/blob/main/docs/rules/device-details/nfet_03v3_nvt/index.rst
5.0v Nmos native device in Deep-Nwell. base cell: PcMos18Finger model:`sky130_fd_pr__nfet_05v0_nvt` Cross-section: https://github.com/google/skywater-pdk/blob/main/docs/rules/device-details/nfet_05v0_nvt/index.rst
Replace cloned Pcells with recent ones.
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Fixes #27