build.plat: strip internal attributes from Verilog output.

Although useful for debugging, most external tools often complain
about such attributes (with notable exception of Vivado). As such,
it is better to emit Verilog with these attributes into a separate
file such as `design.debug.v` and only emit the attributes that were
explicitly placed by the user to `design.v`.

This still leaves the (*init*) attribute. See #220 for details.

nmigen/back/verilog.py

@@ -21,14 +21,18 @@ def _yosys_version():
     return tuple(map(int, tag.split("."))), offset
 
 
-def _convert_il_text(il_text, strip_src):
+def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False):
     version, offset = _yosys_version()
     if version < (0, 9):
         raise YosysError("Yosys %d.%d is not suppored", *version)
 
     attr_map = []
-    if strip_src:
+    if strip_internal_attrs:
+        attr_map.append("-remove generator")
+        attr_map.append("-remove top")
         attr_map.append("-remove src")
+        attr_map.append("-remove nmigen.hierarchy")
+        attr_map.append("-remove nmigen.decoding")
 
     script = """
 # Convert nMigen's RTLIL to readable Verilog.
@@ -41,10 +45,13 @@ def _convert_il_text(il_text, strip_src):
 proc_dff
 proc_clean
 memory_collect
-attrmap {}
+attrmap {attr_map}
+attrmap -modattr {attr_map}
 write_verilog -norename
-""".format(il_text, " ".join(attr_map),
-           prune="# " if version == (0, 9) and offset == 0 else "")
+""".format(rtlil_text,
+        prune="# " if version == (0, 9) and offset == 0 else "",
+        attr_map=" ".join(attr_map),
+    )
 
     popen = subprocess.Popen([require_tool("yosys"), "-q", "-"],
         stdin=subprocess.PIPE,
@@ -58,11 +65,11 @@ def _convert_il_text(il_text, strip_src):
         return verilog_text
 
 
-def convert_fragment(*args, strip_src=False, **kwargs):
-    il_text, name_map = rtlil.convert_fragment(*args, **kwargs)
-    return _convert_il_text(il_text, strip_src), name_map
+def convert_fragment(*args, strip_internal_attrs=False, **kwargs):
+    rtlil_text, name_map = rtlil.convert_fragment(*args, **kwargs)
+    return _convert_rtlil_text(rtlil_text, strip_internal_attrs), name_map
 
 
-def convert(*args, strip_src=False, **kwargs):
-    il_text = rtlil.convert(*args, **kwargs)
-    return _convert_il_text(il_text, strip_src)
+def convert(*args, strip_internal_attrs=False, **kwargs):
+    rtlil_text = rtlil.convert(*args, **kwargs)
+    return _convert_rtlil_text(rtlil_text, strip_internal_attrs)

nmigen/build/plat.py

@@ -272,12 +272,16 @@ def toolchain_prepare(self, fragment, name, **kwargs):
         # and to incorporate the nMigen version into generated code.
         autogenerated = "Automatically generated by nMigen {}. Do not edit.".format(__version__)
 
-        name_map = None
-        def emit_design(backend):
-            nonlocal name_map
-            backend_mod = {"rtlil": rtlil, "verilog": verilog}[backend]
-            design_text, name_map = backend_mod.convert_fragment(fragment, name=name)
-            return design_text
+        rtlil_text, name_map = rtlil.convert_fragment(fragment, name=name)
+
+        def emit_rtlil():
+            return rtlil_text
+
+        def emit_verilog():
+            return verilog._convert_rtlil_text(rtlil_text, strip_internal_attrs=True)
+
+        def emit_debug_verilog():
+            return verilog._convert_rtlil_text(rtlil_text, strip_internal_attrs=False)
 
         def emit_commands(format):
             commands = []
@@ -341,7 +345,9 @@ def render(source, origin):
             return compiled.render({
                 "name": name,
                 "platform": self,
-                "emit_design": emit_design,
+                "emit_rtlil": emit_rtlil,
+                "emit_verilog": emit_verilog,
+                "emit_debug_verilog": emit_debug_verilog,
                 "emit_commands": emit_commands,
                 "get_tool": get_tool,
                 "get_override": get_override,

nmigen/vendor/lattice_ecp5.py

@@ -101,7 +101,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         **TemplatedPlatform.build_script_templates,
         "{{name}}.il": r"""
             # {{autogenerated}}
-            {{emit_design("rtlil")}}
+            {{emit_rtlil()}}
         """,
         "{{name}}.ys": r"""
             # {{autogenerated}}
@@ -182,7 +182,11 @@ class LatticeECP5Platform(TemplatedPlatform):
         """,
         "{{name}}.v": r"""
             /* {{autogenerated}} */
-            {{emit_design("verilog")}}
+            {{emit_verilog()}}
+        """,
+        "{{name}}.debug.v": r"""
+            /* {{autogenerated}} */
+            {{emit_debug_verilog()}}
         """,
         "{{name}}.tcl": r"""
             prj_project new -name {{name}} -impl impl -impl_dir top_impl \

nmigen/vendor/lattice_ice40.py

@@ -105,7 +105,7 @@ class LatticeICE40Platform(TemplatedPlatform):
         **TemplatedPlatform.build_script_templates,
         "{{name}}.il": r"""
             # {{autogenerated}}
-            {{emit_design("rtlil")}}
+            {{emit_rtlil()}}
         """,
         "{{name}}.ys": r"""
             # {{autogenerated}}
@@ -196,7 +196,11 @@ class LatticeICE40Platform(TemplatedPlatform):
         """,
         "{{name}}.v": r"""
             /* {{autogenerated}} */
-            {{emit_design("verilog")}}
+            {{emit_verilog()}}
+        """,
+        "{{name}}.debug.v": r"""
+            /* {{autogenerated}} */
+            {{emit_debug_verilog()}}
         """,
         "{{name}}_lse.prj": r"""
             # {{autogenerated}}

nmigen/vendor/xilinx_7series.py

@@ -63,7 +63,11 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         """,
         "{{name}}.v": r"""
             /* {{autogenerated}} */
-            {{emit_design("verilog")}}
+            {{emit_verilog()}}
+        """,
+        "{{name}}.debug.v": r"""
+            /* {{autogenerated}} */
+            {{emit_debug_verilog()}}
         """,
         "{{name}}.tcl": r"""
             # {{autogenerated}}

nmigen/vendor/xilinx_spartan_3_6.py

@@ -93,7 +93,11 @@ def family(self):
         """,
         "{{name}}.v": r"""
             /* {{autogenerated}} */
-            {{emit_design("verilog")}}
+            {{emit_verilog()}}
+        """,
+        "{{name}}.debug.v": r"""
+            /* {{autogenerated}} */
+            {{emit_debug_verilog()}}
         """,
         "{{name}}.prj": r"""
             # {{autogenerated}}