VexRiscv_Ultra96

• VexRiscv_Ultra96
• VexRiscv core generation
• Vivado Design
• Run RISC-V on standalone mode
• Run RISC-V from Petalinux
• Crosscompile C code for RISC-V
• Export as Vitis platform

Implementation of VexRiscv with rv32imfac architecture on Ultra96-V2.
Environment:

• Ubuntu 18.04
• Ultra96-V2
• Vivado/Vitis/Petalinux 2020.2

VexRiscv core generation

In this project we generate RISC-V core with rv32imfac architecture in VexRiscv.
See coredef/README.md about the detail of core generation and definiton GenSignate.scala.

Vivado Design

Vivado Project is located ./vivado/riscv_base_prj.
For subsequent process, you need to export riscv_base_prj.xsa in vivado because this file is too large to upload.
vivado/README.md describes the guide to create vivado design from scratch.

Run RISC-V on standalone mode

Test floating point operations on RISC-V cores in standalone mode.

See vitis_standalone/README.md about the detail.

Run RISC-V from Petalinux

Test floating point operations on RISC-V cores from petalinux.

See petalinux/README.md about the detail.

Crosscompile C code for RISC-V

Setup crosscompiler with crosstool-NG.
See crosscompile/README.md about the detail.

Export as Vitis platform

Export RISC-V design and petalinux environment as Vitis platform.
See export_vitis/README.md about the detail.
This platform is used base project for Vertical-Beach/ai-edge-contest-5