[top] Integrate ast into FPGA

hw/ip/prim_generic/rtl/prim_generic_clock_buf.sv

@@ -4,7 +4,9 @@
 
 `include "prim_assert.sv"
 
-module prim_generic_clock_buf (
+module prim_generic_clock_buf #(
+  parameter bit NoFpgaBuf = 1'b0 // serves no function in generic
+) (
   input clk_i,
   output logic clk_o
 );

hw/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv

@@ -2,14 +2,21 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-module prim_xilinx_clock_buf (
+module prim_xilinx_clock_buf #(
+  parameter bit NoFpgaBuf = 1'b0
+) (
   input clk_i,
   output logic clk_o
 );
 
-  BUFG bufg_i (
-    .I(clk_i),
-    .O(clk_o)
-  );
+  if (NoFpgaBuf) begin : gen_no_fpga_buf
+    assign clk_o = clk_i;
+  end else begin : gen_fpga_buf
+    BUFG bufg_i (
+      .I(clk_i),
+      .O(clk_o)
+    );
+  end
+
 
 endmodule

hw/top_earlgrey/chip_earlgrey_cw310.core

@@ -9,6 +9,7 @@ filesets:
     depend:
       - lowrisc:systems:top_earlgrey:0.1
       - lowrisc:systems:top_earlgrey_pkg
+      - lowrisc:systems:ast
       - lowrisc:systems:padring
     files:
       - rtl/clkgen_xil7series.sv
@@ -53,6 +54,9 @@ parameters:
     datatype: str
     paramtype: vlogdefine
     description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
+  AST_BYPASS_CLK:
+    datatype: bool
+    paramtype: vlogdefine
 
 targets:
   default: &default_target
@@ -71,6 +75,7 @@ targets:
       - BootRomInitFile
       - OtpCtrlMemInitFile
       - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
+      - AST_BYPASS_CLK=true
     tools:
       vivado:
         part: "xc7k410tfbg676-1" # CW310 with K410T

hw/top_earlgrey/chip_earlgrey_nexysvideo.core

@@ -10,6 +10,7 @@ filesets:
       - lowrisc:systems:top_earlgrey:0.1
       - lowrisc:systems:top_earlgrey_pkg
       - lowrisc:systems:padring
+      - lowrisc:systems:ast
       - lowrisc:tool:chip_earlgrey_nexysvideo_size_check
     files:
       - rtl/clkgen_xil7series.sv

hw/top_earlgrey/data/clocks.xdc

@@ -16,16 +16,15 @@ set clks_aon_unbuf [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT2]]
 
 set u_pll clkgen/pll
 set u_div2 top_*/u_clkmgr_aon/u_no_scan_io_div2_div
-create_generated_clock -name clk_io_div2 -source [get_pin ${u_pll}/CLKOUT0] -divide_by 2 [get_pin ${u_div2}/u_clk_div_buf/gen_xilinx.u_impl_xilinx/bufg_i/O]
+create_generated_clock -name clk_io_div2 -source [get_pin ${u_pll}/CLKOUT0] -divide_by 2 [get_pin ${u_div2}/u_clk_div_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.bufg_i/O]
 
 set u_div4 top_*/u_clkmgr_aon/u_no_scan_io_div4_div
-create_generated_clock -name clk_io_div4 -source [get_pin ${u_pll}/CLKOUT0] -divide_by 4 [get_pin ${u_div4}/u_clk_div_buf/gen_xilinx.u_impl_xilinx/bufg_i/O]
+create_generated_clock -name clk_io_div4 -source [get_pin ${u_pll}/CLKOUT0] -divide_by 4 [get_pin ${u_div4}/u_clk_div_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.bufg_i/O]
 
 ## JTAG and SPI clocks
-create_clock -add -name lc_jtag_tck -period 100.00 -waveform {0 5} [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_lc/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/bufg_i/O]
-create_clock -add -name rv_jtag_tck -period 100.00 -waveform {0 5} [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/bufg_i/O]
-create_clock -add -name clk_spi_in  -period 100.00 -waveform {0 5} [get_pin top_*/u_spi_device/u_clk_spi_in_buf/gen_xilinx.u_impl_xilinx/bufg_i/O]
-create_clock -add -name clk_spi_out -period 100.00 -waveform {0 5} [get_pin top_*/u_spi_device/u_clk_spi_out_buf/gen_xilinx.u_impl_xilinx/bufg_i/O]
+create_clock -add -name lc_jtag_tck -period 100.00 -waveform {0 5} [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_lc/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.bufg_i/O]
+create_clock -add -name rv_jtag_tck -period 100.00 -waveform {0 5} [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.bufg_i/O]
+create_clock -add -name clk_spi_in  -period 100.00 -waveform {0 5} [get_pin top_*/u_spi_device/u_clk_spi_in_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.bufg_i/O]
+create_clock -add -name clk_spi_out -period 100.00 -waveform {0 5} [get_pin top_*/u_spi_device/u_clk_spi_out_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.bufg_i/O]
 
 set_clock_groups -group ${clks_10_unbuf} -group ${clks_48_unbuf} -group ${clks_aon_unbuf} -group clk_io_div2 -group clk_io_div4 -group lc_jtag_tck -group rv_jtag_tck -group clk_spi_in -group clk_spi_out -group sys_clk_pin -asynchronous
-

hw/top_earlgrey/ip/ast/rtl/aon_clk.sv

@@ -38,7 +38,9 @@ aon_osc u_aon_osc (
 
 // Clock & Valid
 ///////////////////////////////////////
-prim_clock_buf u_clk_aon_buf(
+prim_clock_buf #(
+  .NoFpgaBuf(1'b1)
+) u_clk_aon_buf(
   .clk_i ( clk ),
   .clk_o ( clk_src_aon_o )
 );

hw/top_earlgrey/ip/ast/rtl/ast_dft.sv

@@ -68,7 +68,9 @@ end
 logic clk_osc_en;
 assign clk_osc_en = clk_osc_sel && (clk_osc_en_q || clk_osc_aoff);
 
-prim_clock_gating u_clk_osc_ckgt (
+prim_clock_gating #(
+  .NoFpgaGate(1'b1)
+) u_clk_osc_ckgt (
   .clk_i ( clk_io_osc_i ),
   .en_i ( clk_osc_en ),
   .test_en_i ( 1'b0 ),
@@ -104,7 +106,9 @@ end
 logic clk_byp_en;
 assign clk_byp_en = clk_byp_sel && (clk_byp_en_q || clk_byp_aoff);
 
-prim_clock_gating u_clk_byp_ckgt (
+prim_clock_gating #(
+  .NoFpgaGate(1'b1)
+) u_clk_byp_ckgt (
   .clk_i ( clk_ast_ext_i ),
   .en_i ( clk_byp_en ),
   .test_en_i ( 1'b0 ),

hw/top_earlgrey/ip/ast/rtl/io_clk.sv

@@ -38,7 +38,9 @@ io_osc u_io_osc (
 
 // Clock & Valid
 ///////////////////////////////////////
-prim_clock_buf u_clk_io_buf(
+prim_clock_buf #(
+  .NoFpgaBuf(1'b1)
+) u_clk_io_buf(
   .clk_i ( clk ),
   .clk_o ( clk_src_io_o )
 );

hw/top_earlgrey/ip/ast/rtl/io_osc.sv

@@ -54,7 +54,9 @@ assign io_clk_dly = 1'b1;
 ////////////////////////////////////////
 logic clk, en_osc;
 
-prim_clock_gating u_clk_ckgt (
+prim_clock_gating #(
+  .NoFpgaGate(1'b1)
+) u_clk_ckgt (
   .clk_i ( clk_io_ext_i ),
   .en_i ( en_osc ),
   .test_en_i ( 1'b0 ),
@@ -79,7 +81,9 @@ assign en_osc = en_osc_re || en_osc_fe;  // EN -> 1 || EN -> 0
 
 // Clock Output Buffer
 ////////////////////////////////////////
-prim_clock_buf u_buf (
+prim_clock_buf #(
+  .NoFpgaBuf(1'b1)
+) u_buf (
   .clk_i ( clk ),
   .clk_o ( io_clk_o )
 );

hw/top_earlgrey/ip/ast/rtl/sys_clk.sv

@@ -40,7 +40,9 @@ sys_osc u_sys_osc (
 
 // Clock & Valid
 ///////////////////////////////////////
-prim_clock_buf u_clk_sys_buf(
+prim_clock_buf #(
+  .NoFpgaBuf(1'b1)
+) u_clk_sys_buf(
   .clk_i ( clk ),
   .clk_o ( clk_src_sys_o )
 );

hw/top_earlgrey/ip/ast/rtl/sys_osc.sv

@@ -58,7 +58,9 @@ assign sys_clk_dly = 1'b1;
 ////////////////////////////////////////
 logic clk, en_osc;
 
-prim_clock_gating u_clk_ckgt (
+prim_clock_gating #(
+  .NoFpgaGate(1'b1)
+) u_clk_ckgt (
   .clk_i ( clk_sys_ext_i ),
   .en_i ( en_osc ),
   .test_en_i ( 1'b0 ),
@@ -83,7 +85,9 @@ assign en_osc = en_osc_re || en_osc_fe;  // EN -> 1 || EN -> 0
 
 // Clock Output Buffer
 ////////////////////////////////////////
-prim_clock_buf u_buf (
+prim_clock_buf #(
+  .NoFpgaBuf(1'b1)
+) u_buf (
   .clk_i ( clk ),
   .clk_o ( sys_clk_o )
 );

hw/top_earlgrey/ip/ast/rtl/usb_clk.sv

@@ -42,7 +42,9 @@ usb_osc u_usb_osc (
 
 // Clock & Valid
 ///////////////////////////////////////
-prim_clock_buf u_clk_usb_buf(
+prim_clock_buf #(
+  .NoFpgaBuf(1'b1)
+) u_clk_usb_buf(
   .clk_i ( clk ),
   .clk_o ( clk_src_usb_o )
 );

hw/top_earlgrey/ip/ast/rtl/usb_osc.sv

@@ -64,7 +64,9 @@ assign usb_clk_dly = 1'b1;
 ////////////////////////////////////////
 logic clk, en_osc;
 
-prim_clock_gating u_clk_ckgt (
+prim_clock_gating #(
+  .NoFpgaGate(1'b1)
+) u_clk_ckgt (
   .clk_i ( clk_usb_ext_i ),
   .en_i ( en_osc ),
   .test_en_i ( 1'b0 ),
@@ -89,7 +91,9 @@ assign en_osc = en_osc_re || en_osc_fe;  // EN -> 1 || EN -> 0
 
 // Clock Output Buffer
 ////////////////////////////////////////
-prim_clock_buf u_buf (
+prim_clock_buf #(
+  .NoFpgaBuf(1'b1)
+) u_buf (
   .clk_i ( clk ),
   .clk_o ( usb_clk_o )
 );