WIP: Uniquify core VLNVs + promote englishbreakfast to full topgen

.gitignore

@@ -64,13 +64,6 @@ hw/foundry/
 # ROM_EXT signer vendored in dependencies
 sw/host/rom_ext_image_signer/vendored_dependencies
 
-# Autogen files for non-Earlgrey tops
-hw/top_englishbreakfast/**/autogen/
-hw/top_englishbreakfast/ip/alert_handler/dv/alert_handler_env_pkg__params.sv
-hw/top_englishbreakfast/ip/sensor_ctrl/rtl/*
-hw/top_englishbreakfast/ip/xbar_main/xbar_main.core
-hw/top_englishbreakfast/ip/xbar_peri/xbar_peri.core
-
 # Rust Cargo build system files.
 sw/host/**/target
 rust-project.json

BUILD.bazel

@@ -14,8 +14,6 @@ filegroup(
     name = "cores",
     srcs = [
         "check_tool_requirements.core",
-        "topgen.core",
-        "topgen-reg-only.core",
     ],
 )
 

ci/scripts/build-bitstream-vivado.sh

@@ -26,12 +26,10 @@ case x"$TOPLEVEL" in
     xtop_earlgrey)
         HAS_SCRAMBLED_ROM=1
         HAS_OTP=1
-        RUN_TOPGEN_FUSESOC=0
         ;;
     xtop_englishbreakfast)
         HAS_SCRAMBLED_ROM=0
         HAS_OTP=0
-        RUN_TOPGEN_FUSESOC=1
         ;;
     *)
         usage "Unknown toplevel: $TOPLEVEL"
@@ -86,17 +84,10 @@ else
     OTP_ARG=""
 fi
 
-if [ $RUN_TOPGEN_FUSESOC == 1 ]; then
-    util/topgen-fusesoc.py --files-root=. --topname="$TOPLEVEL"
-    FILESET=topgen
-else
-    FILESET=top
-fi
-
 CORE_NAME="lowrisc:systems:chip_${FLAVOUR}_${TARGET}"
 
 fusesoc --verbose --cores-root=. \
-  run --flag=fileset_$FILESET --target=synth --setup --build \
+  run --target=synth --setup --build \
   --build-root="$OBJ_DIR/hw" \
   "$CORE_NAME" \
   --BootRomInitFile="$BOOTROM_VMEM" \

ci/scripts/build-chip-verilator.sh

@@ -18,20 +18,17 @@ tl="$1"
 
 case "$tl" in
     earlgrey)
-        fileset=fileset_top
         fusesoc_core=lowrisc:dv:chip_verilator_sim
         vname=Vchip_sim_tb
         verilator_options="--threads 4"
         make_options="-j 4"
         ;;
     englishbreakfast)
-        fileset=fileset_topgen
         fusesoc_core=lowrisc:systems:chip_englishbreakfast_verilator
         vname=Vchip_englishbreakfast_verilator
         # Englishbreakfast on CI runs on a 2-core CPU
         verilator_options="--threads 2"
         make_options="-j 2"
-        util/topgen-fusesoc.py --files-root=. --topname=top_englishbreakfast
         ;;
     *)
         echo >&2 "Unknown toplevel: $tl"
@@ -49,7 +46,7 @@ mkdir -p "$OBJ_DIR/hw"
 mkdir -p "$BIN_DIR/hw/top_${tl}"
 
 fusesoc --cores-root=. \
-  run --flag=$fileset --target=sim --setup --build \
+  run --target=sim --setup --build \
   --build-root="$OBJ_DIR/hw" \
   $fusesoc_core \
   --verilator_options="${verilator_options}" \

doc/getting_started/setup_fpga.md

@@ -132,7 +132,7 @@ The `--no-export` option of FuseSoC disables copying the source files into the s
 **Only create Vivado project directory by using FuseSoC directly (skipping Bazel invocation).**
 ```sh
 cd $REPO_TOP
-fusesoc --cores-root . run --flag=fileset_top --target=synth --no-export --setup lowrisc:systems:chip_earlgrey_${BOARD}
+fusesoc --cores-root . run --target=synth --no-export --setup lowrisc:systems:chip_earlgrey_${BOARD}
 ```
 
 You can then navigate to the created project directory, and open Vivado

hw/Makefile

@@ -46,7 +46,7 @@ IPS ?= aes           \
        uart          \
        usbdev
 
-TOPS ?= top_darjeeling top_earlgrey
+TOPS ?= top_darjeeling top_earlgrey top_englishbreakfast
 
 USE_BUFFER ?= 0
 

hw/top_earlgrey/ip_autogen/clkmgr/dv/sva/clkmgr_pwrmgr_sva_if.core → hw/dv/sv/mgr_lib/clkmgr_pwrmgr_sva_if.core

@@ -4,6 +4,7 @@ CAPI=2:
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:clkmgr_pwrmgr_sva_if:0.1"
 description: "CLKMGR to PWRMGR assertion interface."
+
 filesets:
   files_dv:
     depend:

hw/ip_templates/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core → hw/dv/sv/mgr_lib/pwrmgr_rstmgr_sva_if.core

@@ -4,10 +4,10 @@ CAPI=2:
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:pwrmgr_rstmgr_sva_if:0.1"
 description: "PWRMGR to RSTMGR assertion interface."
+
 filesets:
   files_dv:
     depend:
-      - lowrisc:ip_interfaces:pwrmgr_pkg
       - lowrisc:prim:assert
     files:
       - pwrmgr_rstmgr_sva_if.sv

hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv → hw/dv/sv/mgr_lib/pwrmgr_rstmgr_sva_if.sv

@@ -5,9 +5,9 @@
 // This has some assertions that check the inputs from rstmgr react according to
 // the pwrmgr outputs. The rstmgr inputs are generated by the base sequences, but
 // these assertions will also be useful at full chip level.
-interface pwrmgr_rstmgr_sva_if
-  import pwrmgr_pkg::*, pwrmgr_reg_pkg::*;
-(
+interface pwrmgr_rstmgr_sva_if #(
+  parameter int unsigned PowerDomains = 2
+) (
   input logic                    clk_i,
   input logic                    rst_ni,
   input logic                    clk_slow_i,

hw/ip/lc_ctrl/lc_ctrl.core

@@ -21,7 +21,7 @@ filesets:
       - lowrisc:ip:otp_ctrl_pkg
       - lowrisc:ip:kmac_pkg
       - lowrisc:ip:rv_dm
-      - lowrisc:ip_interfaces:alert_handler_reg
+      - lowrisc:ip_interfaces:alert_handler_pkg
     files:
       - rtl/lc_ctrl_regs_reg_top.sv
       - rtl/lc_ctrl_dmi_reg_top.sv

hw/ip/prim/prim_flop_2sync.core

@@ -10,6 +10,10 @@ filesets:
     depend:
       - lowrisc:prim:prim_pkg
       - lowrisc:prim:primgen
+      # TODO: This hack should go away with upstream fusesoc support. The
+      # generic prim_generic_flop_2sync depends on prim:flop, but the generator
+      # does not appear to run recursively.
+      - lowrisc:prim:flop
 
   files_verilator_waiver:
     depend:

hw/ip/prim/prim_mubi.core

@@ -16,8 +16,8 @@ filesets:
       - lowrisc:prim:assert
       - lowrisc:prim:buf
       - lowrisc:prim:flop
+      - lowrisc:prim:mubi_pkg
     files:
-      - rtl/prim_mubi_pkg.sv
       - rtl/prim_mubi4_sender.sv
       - rtl/prim_mubi4_sync.sv
       - rtl/prim_mubi4_dec.sv

hw/ip/prim/prim_mubi_pkg.core

@@ -0,0 +1,45 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+# PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+#
+#    util/design/gen-mubi.py
+#
+name: "lowrisc:prim:mubi_pkg:0.1"
+description: "Multibit types and functions"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim:assert
+    files:
+      - rtl/prim_mubi_pkg.sv
+    file_type: systemVerilogSource
+
+  files_verilator_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+
+  files_ascentlint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+    files:
+      - lint/prim_mubi.waiver
+    file_type: waiver
+
+  files_veriblelint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+
+targets:
+  default: &default_target
+    filesets:
+      - tool_verilator   ? (files_verilator_waiver)
+      - tool_ascentlint  ? (files_ascentlint_waiver)
+      - tool_veriblelint ? (files_veriblelint_waiver)
+      - files_rtl

hw/ip/prim_generic/prim_generic_flash.core

@@ -13,7 +13,7 @@ filesets:
       - "fileset_partner  ? (partner:systems:ast_pkg)"
       - "!fileset_partner ? (lowrisc:systems:ast_pkg)"
       - lowrisc:ip_interfaces:flash_ctrl_pkg
-      - lowrisc:ip:flash_ctrl_prim_reg_top
+      - lowrisc:ip_interfaces:flash_ctrl_prim_reg_top
     files:
       - rtl/prim_generic_flash_bank.sv
       - rtl/prim_generic_flash.sv

hw/ip/tlul/headers.core

@@ -10,7 +10,7 @@ filesets:
     depend:
       - lowrisc:constants:top_pkg
       - lowrisc:prim:secded
-      - lowrisc:prim:mubi
+      - lowrisc:prim:mubi_pkg
     files:
       - rtl/tlul_pkg.sv
     file_type: systemVerilogSource

hw/ip_templates/alert_handler/alert_handler.core.tpl

@@ -4,14 +4,12 @@ CAPI=2:
 # SPDX-License-Identifier: Apache-2.0
 name: ${instance_vlnv("lowrisc:ip:alert_handler:0.1")}
 description: "Alert Handler"
-virtual:
-  - lowrisc:ip_interfaces:alert_handler
 
 filesets:
   files_rtl:
     depend:
-      - lowrisc:ip:alert_handler_component
-      - ${instance_vlnv("lowrisc:ip_interfaces:alert_handler_reg:0.1")}
+      - ${instance_vlnv("lowrisc:ip:alert_handler_component:0.1")}
+      - ${instance_vlnv("lowrisc:ip:alert_handler_reg:0.1")}
     file_type: systemVerilogSource
 
 parameters:

hw/ip_templates/alert_handler/alert_handler_component.core → hw/ip_templates/alert_handler/alert_handler_component.core.tpl

@@ -2,7 +2,7 @@ CAPI=2:
 # Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:ip:alert_handler_component:0.1"
+name: ${instance_vlnv("lowrisc:ip:alert_handler_component:0.1")}
 description: "Alert Handler component without the CSRs"
 
 filesets:
@@ -17,9 +17,8 @@ filesets:
       - lowrisc:prim:buf
       - lowrisc:prim:mubi
       - lowrisc:prim:sparse_fsm
-      - lowrisc:ip_interfaces:alert_handler_reg
+      - ${instance_vlnv("lowrisc:ip:alert_handler_reg")}
     files:
-      - rtl/alert_pkg.sv
       - rtl/alert_handler_reg_wrap.sv
       - rtl/alert_handler_lpg_ctrl.sv
       - rtl/alert_handler_class.sv

hw/ip_templates/alert_handler/alert_handler_pkg.core.tpl

@@ -0,0 +1,44 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: ${instance_vlnv("lowrisc:ip:alert_handler_pkg:0.1")}
+description: "Alert Handler constants in packages"
+virtual:
+  - "lowrisc:ip_interfaces:alert_handler_pkg"
+
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:tlul:headers
+    files:
+      - rtl/alert_handler_reg_pkg.sv
+      - rtl/alert_pkg.sv
+    file_type: systemVerilogSource
+
+  files_verilator_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+      - lowrisc:lint:comportable
+
+  files_ascentlint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+      - lowrisc:lint:comportable
+
+  files_veriblelint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+      - lowrisc:lint:comportable
+
+
+targets:
+  default: &default_target
+    filesets:
+      - tool_verilator   ? (files_verilator_waiver)
+      - tool_ascentlint  ? (files_ascentlint_waiver)
+      - tool_veriblelint ? (files_veriblelint_waiver)
+      - files_rtl

hw/ip_templates/alert_handler/alert_handler_reg.core.tpl

@@ -4,18 +4,15 @@ CAPI=2:
 # SPDX-License-Identifier: Apache-2.0
 name: ${instance_vlnv("lowrisc:ip:alert_handler_reg:0.1")}
 description: "Auto-generated alert handler register sources"
-virtual:
-  - "lowrisc:ip_interfaces:alert_handler_reg"
 
 filesets:
   files_rtl:
     depend:
-      - lowrisc:tlul:headers
       - lowrisc:prim:subreg
       - lowrisc:ip:tlul
       - lowrisc:prim:subreg
+      - ${instance_vlnv("lowrisc:ip:alert_handler_pkg")}
     files:
-      - rtl/alert_handler_reg_pkg.sv
       - rtl/alert_handler_reg_top.sv
     file_type: systemVerilogSource
 

hw/ip_templates/alert_handler/data/alert_handler.hjson.tpl

@@ -121,6 +121,8 @@ chars = ['A', 'B', 'C', 'D', 'E', 'F', 'G', 'H']
     { name: "N_ESC_SEV",
       desc: "Number of escalation severities",
       type: "int",
+      # NOTE: If this value is to be changed, ensure all IPs with
+      # prim_esc_receiver get updated as well.
       default: "4",
       local: "true"
     },
@@ -139,6 +141,8 @@ chars = ['A', 'B', 'C', 'D', 'E', 'F', 'G', 'H']
     { name: "PING_CNT_DW",
       desc: "Width of ping counter",
       type: "int",
+      # NOTE: If this value is to be changed, ensure all IPs with
+      # prim_esc_receiver get updated as well.
       default: "16",
       local: "true"
     },

hw/ip_templates/alert_handler/data/alert_handler.tpldesc.hjson

@@ -51,5 +51,11 @@
       type: "object"
       default: []
     }
+    {
+      name: "top_pkg_vlnv"
+      desc: "Provides the VLNV for the top_pkg used by this clkmgr"
+      type: "string"
+      default: "lowrisc:constants:top_pkg"
+    }
   ]
 }

hw/ip_templates/alert_handler/dv/alert_handler_sim.core.tpl

@@ -13,8 +13,8 @@ filesets:
   files_dv:
     depend:
       - lowrisc:dv:ralgen
-      - lowrisc:dv:alert_handler_tb
-      - lowrisc:dv:alert_handler_cov
+      - ${instance_vlnv("lowrisc:dv:alert_handler_tb:0.1")}
+      - ${instance_vlnv("lowrisc:dv:alert_handler_cov:0.1")}
       - ${instance_vlnv("lowrisc:dv:alert_handler_sva:0.1")}
     file_type: systemVerilogSource
 

hw/ip_templates/alert_handler/dv/cov/alert_handler_cov.core → hw/ip_templates/alert_handler/dv/cov/alert_handler_cov.core.tpl

@@ -2,12 +2,12 @@ CAPI=2:
 # Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:dv:alert_handler_cov"
+name: ${instance_vlnv("lowrisc:dv:alert_handler_cov:0.1")}
 description: "ALERT_HANDLER cov bind files"
 filesets:
   files_dv:
     depend:
-      - lowrisc:ip:alert_handler_component  # import alert_pkg
+      - ${instance_vlnv("lowrisc:ip:alert_handler_component:0.1")}  # import alert_pkg
       - lowrisc:dv:dv_utils
     files:
       - alert_handler_cov_bind.sv