[hw,pwm,racl] Add RACL support to PWM

Signed-off-by: Robert Schilling <[email protected]>
lowRISC · Dec 26, 2024 · e9ce170 · e9ce170
1 parent 6199a0c
commit e9ce170
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Showing 6 changed files with 307 additions and 83 deletions.
diff --git a/hw/ip/pwm/data/pwm.hjson b/hw/ip/pwm/data/pwm.hjson
@@ -31,7 +31,7 @@
     {clock: "clk_core_i", reset: "rst_core_ni"}
   ]
   bus_interfaces: [
-    { protocol: "tlul", direction: "device" }
+    { protocol: "tlul", direction: "device", racl_support: true }
   ],
   regwidth: "32",
   param_list: [
@@ -87,6 +87,37 @@
       desc: "End-to-end bus integrity scheme."
     }
   ]
+  inter_signal_list: [
+    { struct:  "racl_policy_vec",
+      type:    "uni",
+      name:    "racl_policies",
+      act:     "rcv",
+      package: "top_racl_pkg",
+      desc:    '''
+        Policy vector distributed to the subscribing RACL IPs.
+      '''
+    }
+    { struct:  "logic",
+      type:    "uni",
+      name:    "racl_error",
+      act:     "req",
+      width  : "1",
+      desc:    '''
+        RACL error indication signal.
+        If 1, the error log contains valid information.
+      '''
+    }
+    { struct:  "racl_error_log",
+      type:    "uni",
+      name:    "racl_error_log",
+      act:     "req",
+      width:   "1"
+      package: "top_racl_pkg",
+      desc:    '''
+        RACL error log information of this module.
+      '''
+    }
+  ],
   registers: [
     { name: "REGWEN",
       desc: "Register write enable for all control registers",

diff --git a/hw/ip/pwm/doc/interfaces.md b/hw/ip/pwm/doc/interfaces.md
@@ -16,9 +16,12 @@ Referring to the [Comportable guideline for peripheral device functionality](htt
 
 ## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling)
 
-| Port Name   | Package::Struct   | Type    | Act   |   Width | Description   |
-|:------------|:------------------|:--------|:------|--------:|:--------------|
-| tl          | tlul_pkg::tl      | req_rsp | rsp   |       1 |               |
+| Port Name      | Package::Struct               | Type    | Act   |   Width | Description                                                                   |
+|:---------------|:------------------------------|:--------|:------|--------:|:------------------------------------------------------------------------------|
+| racl_policies  | top_racl_pkg::racl_policy_vec | uni     | rcv   |       1 | Policy vector distributed to the subscribing RACL IPs.                        |
+| racl_error     | logic                         | uni     | req   |       1 | RACL error indication signal. If 1, the error log contains valid information. |
+| racl_error_log | top_racl_pkg::racl_error_log  | uni     | req   |       1 | RACL error log information of this module.                                    |
+| tl             | tlul_pkg::tl                  | req_rsp | rsp   |       1 |                                                                               |
 
 ## Security Alerts
 

diff --git a/hw/ip/pwm/rtl/pwm.sv b/hw/ip/pwm/rtl/pwm.sv
@@ -7,9 +7,12 @@
 module pwm
   import pwm_reg_pkg::*;
 #(
-  parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
-  parameter int PhaseCntDw = 16,
-  parameter int BeatCntDw = 27
+  parameter logic [NumAlerts-1:0] AlertAsyncOn         = {NumAlerts{1'b1}},
+  parameter bit                   EnableRacl           = 1'b0,
+  parameter bit                   RaclErrorRsp         = 1'b1,
+  parameter int unsigned          RaclPolicySelVec[23] = '{23{0}},
+  parameter int                   PhaseCntDw           = 16,
+  parameter int                   BeatCntDw            = 27
 ) (
   input                       clk_i,
   input                       rst_ni,
@@ -23,23 +26,35 @@ module pwm
   input  prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
   output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
 
+  // RACL interface
+  input  top_racl_pkg::racl_policy_vec_t  racl_policies_i,
+  output logic                            racl_error_o,
+  output top_racl_pkg::racl_error_log_t   racl_error_log_o,
+
   output logic [NOutputs-1:0] cio_pwm_o,
   output logic [NOutputs-1:0] cio_pwm_en_o
 );
 
   pwm_reg_pkg::pwm_reg2hw_t reg2hw;
   logic [NumAlerts-1:0] alert_test, alerts;
 
-  pwm_reg_top u_reg (
+  pwm_reg_top #(
+    .EnableRacl(EnableRacl),
+    .RaclErrorRsp(RaclErrorRsp),
+    .RaclPolicySelVec(RaclPolicySelVec)
+  ) u_reg (
     .clk_i,
     .rst_ni,
     .clk_core_i,
     .rst_core_ni,
-    .tl_i       (tl_i),
-    .tl_o       (tl_o),
-    .reg2hw     (reg2hw),
+    .tl_i                  (tl_i),
+    .tl_o                  (tl_o),
+    .reg2hw                (reg2hw),
+    .racl_policies_i       (racl_policies_i),
+    .racl_error_o          (racl_error_o),
+    .racl_error_log_o      (racl_error_log_o),
     // SEC_CM: BUS.INTEGRITY
-    .intg_err_o (alerts[0])
+    .intg_err_o            (alerts[0])
   );
 
   assign alert_test = {