[tools,topgen] Enhance validate pass

Add support for added top config attributes. Dive deeper into a few attributes. Left a few TODOs for some attributes, most of these are not yet populated. Part of #25920 Signed-off-by: Guillermo Maturana <[email protected]>
lowRISC · Feb 3, 2025 · b7c8e3d · b7c8e3d
1 parent bd3044e
commit b7c8e3d
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Showing 7 changed files with 268 additions and 18 deletions.
diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson
@@ -11274,7 +11274,7 @@
           type: device
           clock: clk_main_i
           reset: rst_main_ni
-          pipefile: false
+          pipeline: false
           inst_type: soc_proxy
           addr_range:
           [
@@ -11288,7 +11288,6 @@
           ]
           xbar: false
           stub: false
-          pipeline: true
           req_fifo_pass: true
         }
         {

diff --git a/hw/top_darjeeling/data/xbar_main.hjson b/hw/top_darjeeling/data/xbar_main.hjson
@@ -106,7 +106,7 @@
       type:      "device",
       clock:     "clk_main_i",
       reset:     "rst_main_ni",
-      pipefile:  false,
+      pipeline:  false,
     },
     { name:      "hmac",
       type:      "device",

diff --git a/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -403,7 +403,7 @@
       type: device
       clock: clk_main_i
       reset: rst_main_ni
-      pipefile: false
+      pipeline: false
       inst_type: soc_proxy
       addr_range:
       [
@@ -417,7 +417,6 @@
       ]
       xbar: false
       stub: false
-      pipeline: true
       req_fifo_pass: true
     }
     {

diff --git a/hw/top_darjeeling/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_darjeeling/ip/xbar_main/rtl/autogen/xbar_main.sv
@@ -1431,7 +1431,8 @@ end
   tlul_socket_m1 #(
     .HReqDepth (16'h0),
     .HRspDepth (16'h0),
-    .DRspPass  (1'b0),
+    .DReqDepth (4'h0),
+    .DRspDepth (4'h0),
     .M         (4)
   ) u_sm1_53 (
     .clk_i        (clk_main_i),

diff --git a/util/tlgen/README.md b/util/tlgen/README.md
@@ -98,6 +98,7 @@ clock_srcs | optional | group | Remnant from auto-generation scripts. Ignore.
 domain | optional | string | Power domain for the crossbar
 reset_connections | added by tool | group | Generated by topgen. Key is the reset signal inside IP and value is the top reset signal
 addr_spaces | added by tool | list | Generated by topgen. List of address spaces used across all hosts
+inter_signal_list | added by tool | list | Generated by topgen. List of inter signals for this xbar
 
 
 ### Node configuration

diff --git a/util/tlgen/validate.py b/util/tlgen/validate.py
@@ -114,6 +114,9 @@
             'l', "Generated by topgen. List of address spaces used across all "
             "hosts"
         ],
+        'inter_signal_list': [
+            'l', "Generated by topgen. List of inter signals for this xbar"
+        ],
     }
 }
 
@@ -148,7 +151,9 @@ def check_keys(obj: Dict[Any, Any],
         elif k in control["optional"]:
             checker = control["optional"][k]
         elif k in control["added"]:
-            log.warning(prefix + " contains generated key " + k)
+            # TODO(lowrisc/opentitan#26082) change severity depending on
+            # user vs. complete config validation
+            log.info(prefix + " contains generated key " + k)
             checker = control["added"][k]
         else:
             log.warning(prefix + " contains extra key " + k)