[ipgen] Generate cross-module references for top cores

clkmgr, flash_ctrl, pwrmgr, and rstmgr all reference other ipgen cores. To enable simulating with the correct dependencies, have topgen add the correct prefixes for the implementing modules for those virtual references. This *still* isn't complete, since there are other virtual references that are *NOT* ipgen cores. Signed-off-by: Alexander Williams <[email protected]>
lowRISC · Dec 28, 2024 · ae6066e · ae6066e
1 parent db5d95a
commit ae6066e
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Showing 68 changed files with 347 additions and 165 deletions.
diff --git a/hw/ip_templates/clkmgr/clkmgr.core.tpl b/hw/ip_templates/clkmgr/clkmgr.core.tpl
@@ -33,6 +33,12 @@ filesets:
       - rtl/clkmgr_trans.sv
     file_type: systemVerilogSource
 
+% if len(pwrmgr_instance_name) > 0:
+  files_top_lint:
+    depend:
+      - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})"
+% endif
+
   files_verilator_waiver:
     depend:
       # common waivers
@@ -63,6 +69,10 @@ targets:
 
   lint:
     <<: *default_target
+% if len(pwrmgr_instance_name) > 0:
+    filesets_append:
+      - files_top_lint
+% endif
     default_tool: verilator
     parameters:
       - SYNTHESIS=true

diff --git a/hw/ip_templates/clkmgr/data/clkmgr.tpldesc.hjson b/hw/ip_templates/clkmgr/data/clkmgr.tpldesc.hjson
@@ -16,10 +16,10 @@
       default: {
         io: {
           name: "io"
-	  aon:  "False"
-	  freq: "96000000"
-	  ref:  "false"
-	}
+          aon:  "False"
+          freq: "96000000"
+          ref:  "false"
+        }
       }
     }
     {
@@ -29,12 +29,12 @@
       default: {
         main: {
           name: "io_div4"
-	  aon:  "False"
-	  freq: "24000000"
-	  ref:  "false"
-	  div:  "4"
-	  src:  "io"
-	}
+          aon:  "False"
+          freq: "24000000"
+          ref:  "false"
+          div:  "4"
+          src:  "io"
+        }
       }
     }
     {
@@ -43,12 +43,12 @@
       type: "object"
       default: {
         hint_clks: {
-	  name: "clk_main_aes"
-	  signal: {
-	    src_name: "main"
-	    endpoint_ip: "aes"
-	  }
-	}
+          name: "clk_main_aes"
+          signal: {
+            src_name: "main"
+            endpoint_ip: "aes"
+          }
+        }
       }
     }
     {
@@ -73,11 +73,11 @@
       type: "object"
       default: {
         intf: {
-	  ep: [
-	    "clk1"
-	    "clk2"
-	  ]
-	}
+          ep: [
+            "clk1"
+            "clk2"
+          ]
+        }
       }
     }
     {
@@ -92,5 +92,11 @@
       type: "bool"
       default: "1"
     }
+    {
+      name: "pwrmgr_instance_name"
+      desc: "Instance name for the pwrmgr dependencies, if available"
+      type: "string"
+      default: ""
+    }
   ]
 }
diff --git a/hw/ip_templates/clkmgr/dv/clkmgr_sim.core.tpl b/hw/ip_templates/clkmgr/dv/clkmgr_sim.core.tpl
@@ -18,12 +18,21 @@ filesets:
       - cov/clkmgr_cov_bind.sv
     file_type: systemVerilogSource
 
+% if len(pwrmgr_instance_name) > 0:
+  files_top_sim:
+    depend:
+      - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})"
+%endif
+
 targets:
   sim: &sim_target
     toplevel: tb
     filesets:
       - files_rtl
       - files_dv
+% if len(pwrmgr_instance_name) > 0:
+      - files_top_sim
+% endif
     default_tool: vcs
 
   lint:

diff --git a/hw/ip_templates/clkmgr/dv/clkmgr_sim_cfg.hjson.tpl b/hw/ip_templates/clkmgr/dv/clkmgr_sim_cfg.hjson.tpl
@@ -15,7 +15,7 @@
   tool: vcs
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: ${instance_vlnv("lowrisc:dv:clkmgr_sim_top:0.1")}
+  fusesoc_core: ${instance_vlnv("lowrisc:dv:clkmgr_sim:0.1")}
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/clkmgr_testplan.hjson"

diff --git a/hw/ip_templates/flash_ctrl/data/flash_ctrl.tpldesc.hjson b/hw/ip_templates/flash_ctrl/data/flash_ctrl.tpldesc.hjson
@@ -87,5 +87,11 @@
       type: "int"
       default: "1048576"
     }
+    {
+      name: "pwrmgr_instance_name"
+      desc: "Instance name for the pwrmgr dependencies, if available"
+      type: "string"
+      default: ""
+    }
   ]
 }
diff --git a/hw/ip_templates/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson.tpl b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson.tpl
@@ -12,7 +12,7 @@
   tb: tb
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: ${instance_vlnv("lowrisc:dv:flash_ctrl_sim_top:0.1")}
+  fusesoc_core: ${instance_vlnv("lowrisc:dv:flash_ctrl_sim:0.1")}
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/flash_ctrl_testplan.hjson"

diff --git a/hw/ip_templates/flash_ctrl/dv/flash_ctrl_sim.core.tpl b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_sim.core.tpl
@@ -22,6 +22,12 @@ filesets:
       - tb/tb.sv
     file_type: systemVerilogSource
 
+% if len(pwrmgr_instance_name) > 0:
+  files_top_sim:
+    depend:
+      - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})"
+%endif
+
 targets:
   default: &default_target
     toplevel: tb
@@ -31,7 +37,15 @@ targets:
 
   sim:
     <<: *default_target
+% if len(pwrmgr_instance_name) > 0:
+    filesets_append:
+      - files_top_sim
+% endif
     default_tool: vcs
 
   lint:
     <<: *default_target
+% if len(pwrmgr_instance_name) > 0:
+    filesets_append:
+      - files_top_sim
+% endif
diff --git a/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl b/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl
@@ -46,6 +46,12 @@ filesets:
       - rtl/flash_phy_scramble.sv
     file_type: systemVerilogSource
 
+% if len(pwrmgr_instance_name) > 0:
+  files_top_lint:
+    depend:
+      - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})"
+% endif
+
   files_verilator_waiver:
     depend:
       # common waivers
@@ -87,6 +93,10 @@ targets:
 
   lint:
     <<: *default_target
+% if len(pwrmgr_instance_name) > 0:
+    filesets_append:
+      - files_top_lint
+% endif
     default_tool: verilator
     parameters:
       - SYNTHESIS=true

diff --git a/hw/ip_templates/pwrmgr/data/pwrmgr.tpldesc.hjson b/hw/ip_templates/pwrmgr/data/pwrmgr.tpldesc.hjson
@@ -64,5 +64,17 @@
       type: "int"
       default: "1"
     }
+    {
+      name: "alert_handler_instance_name"
+      desc: "Instance name for the alert_handler dependencies, if available"
+      type: "string"
+      default: ""
+    }
+    {
+      name: "clkmgr_instance_name"
+      desc: "Instance name for the clkmgr dependencies, if available"
+      type: "string"
+      default: ""
+    }
   ]
 }
diff --git a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core.tpl b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core.tpl
@@ -17,13 +17,30 @@ filesets:
       - tb.sv
       - cov/pwrmgr_cov_bind.sv
     file_type: systemVerilogSource
+<%
+    have_files_top_sim = (len(clkmgr_instance_name) > 0 or
+                          len(alert_handler_instance_name) > 0)
+%>\
+% if have_files_top_sim:
+  files_top_sim:
+    depend:
+%   if len(alert_handler_instance_name) > 0:
+      - "fileset_top ? (${instance_vlnv("lowrisc:ip:alert_handler_pkg:0.1", alert_handler_instance_name)})"
+%   endif
+%   if len(clkmgr_instance_name) > 0:
+      - "fileset_top ? (${instance_vlnv("lowrisc:ip:clkmgr_pwrmgr_sva_if:0.1", clkmgr_instance_name)})"
+%   endif
+% endif
 
 targets:
   sim: &sim_target
     toplevel: tb
     filesets:
       - files_rtl
       - files_dv
+% if have_files_top_sim:
+      - files_top_sim
+% endif
     default_tool: vcs
 
   lint:

diff --git a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim_cfg.hjson.tpl b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim_cfg.hjson.tpl
@@ -15,7 +15,7 @@
   tool: vcs
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: ${instance_vlnv("lowrisc:dv:pwrmgr_sim_top:0.1")}
+  fusesoc_core: ${instance_vlnv("lowrisc:dv:pwrmgr_sim:0.1")}
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/pwrmgr_testplan.hjson"

diff --git a/hw/ip_templates/pwrmgr/pwrmgr.core.tpl b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl
@@ -15,6 +15,12 @@ filesets:
       - ${instance_vlnv("lowrisc:ip:pwrmgr_component:0.1")}
     file_type: systemVerilogSource
 
+% if len(alert_handler_instance_name) > 0:
+  files_top_lint:
+    depend:
+      - "fileset_top ? (${instance_vlnv("lowrisc:ip:alert_handler_pkg:0.1", alert_handler_instance_name)})"
+% endif
+
   files_verilator_waiver:
     depend:
       # common waivers
@@ -56,6 +62,10 @@ targets:
 
   lint:
     <<: *default_target
+% if len(alert_handler_instance_name) > 0:
+    filesets_append:
+      - files_top_lint
+% endif
     default_tool: verilator
     parameters:
       - SYNTHESIS=true

diff --git a/hw/ip_templates/rstmgr/data/rstmgr.tpldesc.hjson b/hw/ip_templates/rstmgr/data/rstmgr.tpldesc.hjson
@@ -117,5 +117,17 @@
       type: "bool"
       default: "1"
     }
+    {
+      name: "alert_handler_instance_name"
+      desc: "Instance name for the alert_handler dependencies, if available"
+      type: "string"
+      default: ""
+    }
+    {
+      name: "pwrmgr_instance_name"
+      desc: "Instance name for the pwrmgr dependencies, if available"
+      type: "string"
+      default: ""
+    }
   ]
 }
diff --git a/hw/ip_templates/rstmgr/dv/rstmgr_sim.core.tpl b/hw/ip_templates/rstmgr/dv/rstmgr_sim.core.tpl
@@ -17,13 +17,31 @@ filesets:
       - tb.sv
       - cov/rstmgr_cov_bind.sv
     file_type: systemVerilogSource
+<%
+    have_files_top_sim = (len(alert_handler_instance_name) > 0 or
+                          len(pwrmgr_instance_name) > 0)
+%>\
+% if have_files_top_sim:
+  files_top_sim:
+    depend:
+%   if len(alert_handler_instance_name) > 0:
+      - "fileset_top ? (${instance_vlnv("lowrisc:ip:alert_handler_pkg:0.1", alert_handler_instance_name)})"
+%   endif
+%   if len(pwrmgr_instance_name) > 0:
+      - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})"
+      - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_rstmgr_sva_if:0.1", pwrmgr_instance_name)})"
+%   endif
+% endif
 
 targets:
   sim: &sim_target
     toplevel: tb
     filesets:
       - files_rtl
       - files_dv
+% if have_files_top_sim:
+      - files_top_sim
+% endif
     default_tool: vcs
 
   lint:

diff --git a/hw/ip_templates/rstmgr/dv/rstmgr_sim_cfg.hjson.tpl b/hw/ip_templates/rstmgr/dv/rstmgr_sim_cfg.hjson.tpl
@@ -15,7 +15,7 @@
   tool: vcs
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: ${instance_vlnv("lowrisc:dv:rstmgr_sim_top:0.1")}
+  fusesoc_core: ${instance_vlnv("lowrisc:dv:rstmgr_sim:0.1")}
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/rstmgr_testplan.hjson"

diff --git a/hw/ip_templates/rstmgr/rstmgr.core.tpl b/hw/ip_templates/rstmgr/rstmgr.core.tpl
@@ -30,6 +30,21 @@ filesets:
       - rtl/rstmgr.sv
     file_type: systemVerilogSource
 
+<%
+    have_files_top_lint = (len(alert_handler_instance_name) > 0 or
+                           len(pwrmgr_instance_name) > 0)
+%>\
+% if have_files_top_lint:
+  files_top_lint:
+    depend:
+%   if len(alert_handler_instance_name) > 0:
+      - "fileset_top ? (${instance_vlnv("lowrisc:ip:alert_handler_pkg:0.1", alert_handler_instance_name)})"
+%   endif
+%   if len(pwrmgr_instance_name) > 0:
+      - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})"
+%   endif
+% endif
+
   files_verilator_waiver:
     depend:
       # common waivers
@@ -61,6 +76,10 @@ targets:
 
   lint:
     <<: *default_target
+% if have_files_top_lint:
+    filesets_append:
+      - files_top_lint
+% endif
     default_tool: verilator
     parameters:
       - SYNTHESIS=true