[top,lint] Add special cores for lint, sim for earlgrey

These cores collect the relevant cross-referenced virtual core implementations into the dependency list, so lint is run on the earlgrey-specific configuration for ipgen'd and reggen_top cores. Also fix up the references in the lint configs. Also add top_englishbreakfast to lint targets for englishbreakfast's hjson file. Signed-off-by: Alexander Williams <[email protected]>
lowRISC · Dec 28, 2024 · 67ede0b · 67ede0b
1 parent 6b1adc9
commit 67ede0b
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Showing 23 changed files with 231 additions and 37 deletions.
diff --git a/..._templates/clkmgr/dv/clkmgr_sim_cfg.hjson → ...plates/clkmgr/dv/clkmgr_sim_cfg.hjson.tpl b/..._templates/clkmgr/dv/clkmgr_sim_cfg.hjson → ...plates/clkmgr/dv/clkmgr_sim_cfg.hjson.tpl
@@ -15,7 +15,7 @@
   tool: vcs
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: lowrisc:dv:clkmgr_sim:0.1
+  fusesoc_core: ${instance_vlnv("lowrisc:dv:clkmgr_sim_top:0.1")}
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/clkmgr_testplan.hjson"

diff --git a/hw/ip_templates/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson.tpl b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson.tpl
@@ -12,7 +12,7 @@
   tb: tb
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: ${instance_vlnv("lowrisc:dv:flash_ctrl_sim:0.1")}
+  fusesoc_core: ${instance_vlnv("lowrisc:dv:flash_ctrl_sim_top:0.1")}
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/flash_ctrl_testplan.hjson"

diff --git a/..._templates/pwrmgr/dv/pwrmgr_sim_cfg.hjson → ...plates/pwrmgr/dv/pwrmgr_sim_cfg.hjson.tpl b/..._templates/pwrmgr/dv/pwrmgr_sim_cfg.hjson → ...plates/pwrmgr/dv/pwrmgr_sim_cfg.hjson.tpl
@@ -15,7 +15,7 @@
   tool: vcs
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: lowrisc:dv:pwrmgr_sim:0.1
+  fusesoc_core: ${instance_vlnv("lowrisc:dv:pwrmgr_sim_top:0.1")}
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/pwrmgr_testplan.hjson"

diff --git a/hw/ip_templates/rstmgr/dv/rstmgr_sim_cfg.hjson.tpl b/hw/ip_templates/rstmgr/dv/rstmgr_sim_cfg.hjson.tpl
@@ -15,7 +15,7 @@
   tool: vcs
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: ${instance_vlnv("lowrisc:dv:rstmgr_sim:0.1")}
+  fusesoc_core: ${instance_vlnv("lowrisc:dv:rstmgr_sim_top:0.1")}
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/rstmgr_testplan.hjson"

diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson b/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson
@@ -15,7 +15,7 @@
   tool: vcs
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: lowrisc:dv:clkmgr_sim:0.1
+  fusesoc_core: lowrisc:opentitan:top_darjeeling_clkmgr_sim_top:0.1
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/clkmgr_testplan.hjson"

diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson
@@ -15,7 +15,7 @@
   tool: vcs
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: lowrisc:dv:pwrmgr_sim:0.1
+  fusesoc_core: lowrisc:opentitan:top_darjeeling_pwrmgr_sim_top:0.1
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/pwrmgr_testplan.hjson"

diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson
@@ -15,7 +15,7 @@
   tool: vcs
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: lowrisc:opentitan:top_darjeeling_rstmgr_sim:0.1
+  fusesoc_core: lowrisc:opentitan:top_darjeeling_rstmgr_sim_top:0.1
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/rstmgr_testplan.hjson"

diff --git a/hw/top_darjeeling/lint/top_darjeeling_lint_cfgs.hjson b/hw/top_darjeeling/lint/top_darjeeling_lint_cfgs.hjson
@@ -53,7 +53,7 @@
                   rel_path: "hw/ip/aon_timer/lint/{tool}"
              },
              {    name: ast
-                  fusesoc_core: lowrisc:systems:ast
+                  fusesoc_core: lowrisc:systems:top_darjeeling_ast
                   import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
                   rel_path: "hw/top_darjeeling/ip/ast/lint/{tool}"
                   overrides: [
@@ -293,7 +293,7 @@
                   rel_path: "hw/ip/tlul/adapter_sram/lint/{tool}"
              },
              {    name: sensor_ctrl
-                  fusesoc_core: lowrisc:systems:sensor_ctrl
+                  fusesoc_core: lowrisc:systems:top_darjeeling_sensor_ctrl
                   import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
                   rel_path: "hw/top_darjeeling/ip/sensor_ctrl/lint/{tool}"
              },

diff --git a/hw/top_earlgrey/dv/top_earlgrey_ast_top.core b/hw/top_earlgrey/dv/top_earlgrey_ast_top.core
@@ -0,0 +1,33 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:top_earlgrey_ast_top:0.1"
+description: "Pseudo top-level for Earl Grey's ast"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:opentitan:top_earlgrey_alert_handler_pkg
+      - lowrisc:opentitan:top_earlgrey_clkmgr_pkg
+      - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg
+      - lowrisc:opentitan:top_earlgrey_rstmgr_pkg
+      - lowrisc:opentitan:top_earlgrey_ast
+
+parameters:
+  SYNTHESIS:
+    datatype: bool
+    paramtype: vlogdefine
+
+targets:
+  lint:
+    toplevel: ast
+    filesets:
+      - files_rtl
+    default_tool: verilator
+    parameters:
+      - SYNTHESIS=true
+    tools:
+      verilator:
+        mode: lint-only
+        verilator_options:
+          - "-Wall"  default: &default_target
diff --git a/hw/top_earlgrey/dv/top_earlgrey_clkmgr_sim_top.core b/hw/top_earlgrey/dv/top_earlgrey_clkmgr_sim_top.core
@@ -0,0 +1,40 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:opentitan:top_earlgrey_clkmgr_sim_top:0.1"
+description: "Pseudo top-level for Earl Grey's clkmgr"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg
+      - lowrisc:opentitan:top_earlgrey_clkmgr
+  files_dv:
+    depend:
+      - lowrisc:opentitan:top_earlgrey_clkmgr_sim
+
+parameters:
+  SYNTHESIS:
+    datatype: bool
+    paramtype: vlogdefine
+
+targets:
+  lint:
+    toplevel: clkmgr
+    filesets:
+      - files_rtl
+    default_tool: verilator
+    parameters:
+      - SYNTHESIS=true
+    tools:
+      verilator:
+        mode: lint-only
+        verilator_options:
+          - "-Wall"  default: &default_target
+
+  sim:
+    toplevel: tb
+    filesets:
+      - files_rtl
+      - files_dv
+    default_tool: vcs
diff --git a/hw/top_earlgrey/dv/top_earlgrey_flash_ctrl_sim_top.core b/hw/top_earlgrey/dv/top_earlgrey_flash_ctrl_sim_top.core
@@ -0,0 +1,40 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:opentitan:top_earlgrey_flash_ctrl_sim_top:0.1"
+description: "Pseudo top-level for Earl Grey's flash_ctrl"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg
+      - lowrisc:opentitan:top_earlgrey_flash_ctrl
+  files_dv:
+    depend:
+      - lowrisc:opentitan:top_earlgrey_flash_ctrl_sim
+
+parameters:
+  SYNTHESIS:
+    datatype: bool
+    paramtype: vlogdefine
+
+targets:
+  lint:
+    toplevel: flash_ctrl
+    filesets:
+      - files_rtl
+    default_tool: verilator
+    parameters:
+      - SYNTHESIS=true
+    tools:
+      verilator:
+        mode: lint-only
+        verilator_options:
+          - "-Wall"  default: &default_target
+
+  sim:
+    toplevel: tb
+    filesets:
+      - files_rtl
+      - files_dv
+    default_tool: vcs
diff --git a/hw/top_earlgrey/dv/top_earlgrey_pwrmgr_sim_top.core b/hw/top_earlgrey/dv/top_earlgrey_pwrmgr_sim_top.core
@@ -0,0 +1,41 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:opentitan:top_earlgrey_pwrmgr_sim_top:0.1"
+description: "Pseudo top-level for Earl Grey's pwrmgr"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:opentitan:top_earlgrey_alert_handler_pkg
+      - lowrisc:opentitan:top_earlgrey_pwrmgr
+  files_dv:
+    depend:
+      - lowrisc:opentitan:top_earlgrey_pwrmgr_sim
+      - lowrisc:opentitan:clkmgr_pwrmgr_sva_if
+
+parameters:
+  SYNTHESIS:
+    datatype: bool
+    paramtype: vlogdefine
+
+targets:
+  lint:
+    toplevel: pwrmgr
+    filesets:
+      - files_rtl
+    default_tool: verilator
+    parameters:
+      - SYNTHESIS=true
+    tools:
+      verilator:
+        mode: lint-only
+        verilator_options:
+          - "-Wall"  default: &default_target
+
+  sim:
+    toplevel: tb
+    filesets:
+      - files_rtl
+      - files_dv
+    default_tool: vcs
diff --git a/hw/top_earlgrey/dv/top_earlgrey_rstmgr_sim_top.core b/hw/top_earlgrey/dv/top_earlgrey_rstmgr_sim_top.core
@@ -0,0 +1,41 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:opentitan:top_earlgrey_rstmgr_sim_top:0.1"
+description: "Pseudo top-level for Earl Grey's rstmgr"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg
+      - lowrisc:opentitan:top_earlgrey_rstmgr
+  files_dv:
+    depend:
+      - lowrisc:opentitan:top_earlgrey_pwrmgr_rstmgr_sva_if
+      - lowrisc:opentitan:top_earlgrey_rstmgr_sim
+
+parameters:
+  SYNTHESIS:
+    datatype: bool
+    paramtype: vlogdefine
+
+targets:
+  lint:
+    toplevel: rstmgr
+    filesets:
+      - files_rtl
+    default_tool: verilator
+    parameters:
+      - SYNTHESIS=true
+    tools:
+      verilator:
+        mode: lint-only
+        verilator_options:
+          - "-Wall"  default: &default_target
+
+  sim:
+    toplevel: tb
+    filesets:
+      - files_rtl
+      - files_dv
+    default_tool: vcs
diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson b/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson
@@ -15,7 +15,7 @@
   tool: vcs
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: lowrisc:dv:clkmgr_sim:0.1
+  fusesoc_core: lowrisc:opentitan:top_earlgrey_clkmgr_sim_top:0.1
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/clkmgr_testplan.hjson"

diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson
@@ -12,7 +12,7 @@
   tb: tb
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: lowrisc:opentitan:top_earlgrey_flash_ctrl_sim:0.1
+  fusesoc_core: lowrisc:opentitan:top_earlgrey_flash_ctrl_sim_top:0.1
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/flash_ctrl_testplan.hjson"

diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson
@@ -15,7 +15,7 @@
   tool: vcs
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: lowrisc:dv:pwrmgr_sim:0.1
+  fusesoc_core: lowrisc:opentitan:top_earlgrey_pwrmgr_sim_top:0.1
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/pwrmgr_testplan.hjson"

diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson b/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson
@@ -15,7 +15,7 @@
   tool: vcs
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: lowrisc:opentitan:top_earlgrey_rstmgr_sim:0.1
+  fusesoc_core: lowrisc:opentitan:top_earlgrey_rstmgr_sim_top:0.1
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/rstmgr_testplan.hjson"

diff --git a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson
@@ -48,7 +48,7 @@
                   rel_path: "hw/ip/ascon/lint/{tool}"
              },
              {    name: ast
-                  fusesoc_core: lowrisc:systems:ast
+                  fusesoc_core: lowrisc:dv:top_earlgrey_ast_top
                   import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
                   rel_path: "hw/top_earlgrey/ip/ast/lint/{tool}"
                   overrides: [
@@ -64,7 +64,7 @@
                   rel_path: "hw/ip/entropy_src/lint/{tool}"
              },
              {    name: clkmgr
-                  fusesoc_core: lowrisc:opentitan:top_earlgrey_clkmgr
+                  fusesoc_core: lowrisc:opentitan:top_earlgrey_clkmgr_sim_top
                   import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"],
                   rel_path: "hw/top_earlgrey/ip_autogen/clkmgr/lint/{tool}",
                   overrides: [
@@ -90,7 +90,7 @@
                   rel_path: "hw/ip/edn/lint/{tool}"
              },
              {    name: flash_ctrl
-                  fusesoc_core: lowrisc:opentitan:top_earlgrey_flash_ctrl
+                  fusesoc_core: lowrisc:opentitan:top_earlgrey_flash_ctrl_sim_top
                   import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
                   rel_path: "hw/top_earlgrey/ip_autogen/flash_ctrl/lint/{tool}"
                   overrides: [
@@ -158,7 +158,7 @@
                   ]
              },
              {    name: pinmux
-                  fusesoc_core: lowrisc:ip_interfaces:pinmux
+                  fusesoc_core: lowrisc:opentitan:top_earlgrey_pinmux
                   import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
                   rel_path: "hw/top_earlgrey/ip_autogen/pinmux/lint/{tool}"
                   overrides: [
@@ -180,7 +180,7 @@
                   ]
              },
              {    name: pwrmgr
-                  fusesoc_core: lowrisc:opentitan:top_earlgrey_pwrmgr
+                  fusesoc_core: lowrisc:opentitan:top_earlgrey_pwrmgr_sim_top
                   import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"],
                   rel_path: "hw/top_earlgrey/ip_autogen/pwrmgr/lint/{tool}",
                   overrides: [
@@ -196,7 +196,7 @@
                   rel_path: "hw/ip/rom_ctrl/lint/{tool}"
              },
              {    name: rstmgr
-                  fusesoc_core: lowrisc:opentitan:top_earlgrey_rstmgr
+                  fusesoc_core: lowrisc:opentitan:top_earlgrey_rstmgr_sim_top
                   import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"],
                   rel_path: "hw/top_earlgrey/ip_autogen/rstmgr/lint/{tool}",
                   overrides: [
@@ -283,7 +283,7 @@
                   rel_path: "hw/ip/tlul/adapter_sram/lint/{tool}"
              },
              {    name: sensor_ctrl
-                  fusesoc_core: lowrisc:systems:sensor_ctrl
+                  fusesoc_core: lowrisc:systems:top_earlgrey_sensor_ctrl
                   import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
                   rel_path: "hw/top_earlgrey/ip/sensor_ctrl/lint/{tool}"
              },

diff --git a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson
@@ -15,7 +15,7 @@
   tool: vcs
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: lowrisc:dv:clkmgr_sim:0.1
+  fusesoc_core: lowrisc:opentitan:top_englishbreakfast_clkmgr_sim_top:0.1
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/clkmgr_testplan.hjson"

diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson
@@ -12,7 +12,7 @@
   tb: tb
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: lowrisc:opentitan:top_englishbreakfast_flash_ctrl_sim:0.1
+  fusesoc_core: lowrisc:opentitan:top_englishbreakfast_flash_ctrl_sim_top:0.1
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/flash_ctrl_testplan.hjson"