[NVPTX] Fix 64 bits rotations with large shift values #89399
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Artem-B
approved these changes
Apr 19, 2024
| declare i64 @llvm.fshr.i64(i64, i64, i64) | ||
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| ; SM35: rotl64 | ||
| define i64 @rotl64(i64 %a, i64 %n) { |
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This test should probably be converted to use llvm/utils/update_llc_test_checks.py
We do care about the arguments and the exact instruction sequences here.
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^^^ we still want to improve the test.
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Oh right! Updated with the script now, it was confusing for a little bit because it doesn't understand -march so I had to swap to --mtriple.
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@Artem-B I don't have commit permissions, would you mind landing this? I'll try to follow up with the suggestions when I have time. |
ROTL and ROTR can take a shift amount larger than the element size, in which case the effective shift amount should be the shift amount modulo the element size. This patch adds the modulo step when the shift amount isn't known at compile time. Without it the existing implementation would end up shifting beyond the type size and give incorrect results.
Artem-B
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May 1, 2024
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| ; SM35-NEXT: ld.param.u64 %rd1, [rotate64_param_0]; | ||
| ; SM35-NEXT: { | ||
| ; SM35-NEXT: .reg .b32 %dummy; | ||
| ; SM35-NEXT: mov.b64 {%dummy,%r1}, %rd1; | ||
| ; SM35-NEXT: } | ||
| ; SM35-NEXT: { | ||
| ; SM35-NEXT: .reg .b32 %dummy; | ||
| ; SM35-NEXT: mov.b64 {%r2,%dummy}, %rd1; | ||
| ; SM35-NEXT: } |
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Looks like a minor optimization opportunity for the future -- this could be done as mov.b64 {%r2, %r1}, %rd1.
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ROTL and ROTR can take a shift amount larger than the element size, in which case the effective shift amount should be the shift amount modulo the element size.
This patch adds the modulo step when the shift amount isn't known at compile time. Without it the existing implementation would end up shifting beyond the type size and give incorrect results.
cc @Artem-B