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Backport [RISCV] Graduate Zicond to non-experimental (#79811) #80018

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Jan 30, 2024
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Backport [RISCV] Graduate Zicond to non-experimental (#79811) #80018

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[RISCV] Graduate Zicond to non-experimental (#79811)
asb Jan 30, 2024
8654441
Merge branch 'release/18.x' into 2024q1-riscv-backport-zicond
tstellar Jan 30, 2024
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2 changes: 1 addition & 1 deletion clang/test/CodeGen/RISCV/riscv-func-attr-target.c
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Expand Up @@ -39,7 +39,7 @@ __attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {}
// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,-relax,-zbb,-zfa" }
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }
// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+save-restore,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }
// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zbb,+zicond,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }
// Make sure we append negative features if we override the arch
// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
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16 changes: 8 additions & 8 deletions clang/test/Preprocessor/riscv-target-features.c
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Expand Up @@ -764,6 +764,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICNTR-EXT %s
// CHECK-ZICNTR-EXT: __riscv_zicntr 2000000{{$}}

// RUN: %clang --target=riscv32 \
// RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
// RUN: %clang --target=riscv64 \
// RUN: -march=rv64i_zicond1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
// CHECK-ZICOND-EXT: __riscv_zicond 1000000{{$}}

// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32izicsr2p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICSR-EXT %s
Expand Down Expand Up @@ -1332,14 +1340,6 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s
// CHECK-ZICFILP-EXT: __riscv_zicfilp 4000{{$}}

// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: -march=rv64i_zicond1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
// CHECK-ZICOND-EXT: __riscv_zicond 1000000{{$}}

// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zimop0p1 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZIMOP-EXT %s
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4 changes: 1 addition & 3 deletions llvm/docs/RISCVUsage.rst
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Expand Up @@ -130,6 +130,7 @@ on support follow.
``Zicclsm`` Supported (`See note <#riscv-profiles-extensions-note>`__)
``Ziccrse`` Supported (`See note <#riscv-profiles-extensions-note>`__)
``Zicntr`` (`See Note <#riscv-i2p1-note>`__)
``Zicond`` Supported
``Zicsr`` (`See Note <#riscv-i2p1-note>`__)
``Zifencei`` (`See Note <#riscv-i2p1-note>`__)
``Zihintntl`` Supported
Expand Down Expand Up @@ -234,9 +235,6 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zicfilp``, ``experimental-zicfiss``
LLVM implements the `0.4 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0>`__.

``experimental-zicond``
LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1>`__.

``experimental-ztso``
LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`__ (see Chapter 25). The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document. There are multiple possible mappings, and they are *not* mutually ABI compatible. The mapping LLVM implements is ABI compatible with the default WMO mapping. This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status. User beware.

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1 change: 1 addition & 0 deletions llvm/docs/ReleaseNotes.rst
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Expand Up @@ -181,6 +181,7 @@ Changes to the RISC-V Backend
specification.
* The Smepmp 1.0 extension is now supported.
* ``-mcpu=sifive-p670`` was added.
* Support for the Zicond extension is no longer experimental.

Changes to the WebAssembly Backend
----------------------------------
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3 changes: 1 addition & 2 deletions llvm/lib/Support/RISCVISAInfo.cpp
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Expand Up @@ -128,6 +128,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"zicclsm", {1, 0}},
{"ziccrse", {1, 0}},
{"zicntr", {2, 0}},
{"zicond", {1, 0}},
{"zicsr", {2, 0}},
{"zifencei", {2, 0}},
{"zihintntl", {1, 0}},
Expand Down Expand Up @@ -200,8 +201,6 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zicfilp", {0, 4}},
{"zicfiss", {0, 4}},

{"zicond", {1, 0}},

{"zimop", {0, 1}},

{"ztso", {0, 1}},
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -72,7 +72,7 @@ def FeatureStdExtZicntr
[FeatureStdExtZicsr]>;

def FeatureStdExtZicond
: SubtargetFeature<"experimental-zicond", "HasStdExtZicond", "true",
: SubtargetFeature<"zicond", "HasStdExtZicond", "true",
"'Zicond' (Integer Conditional Operations)">;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
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2 changes: 0 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
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Expand Up @@ -8,8 +8,6 @@
//
// This file describes the RISC-V instructions from the standard Integer
// Conditional operations extension (Zicond).
// This version is still experimental as the 'Zicond' extension hasn't been
// ratified yet. It is based on v1.0-rc1 of the specification.
//
//===----------------------------------------------------------------------===//

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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -84,7 +84,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s
; RUN: llc -mtriple=riscv32 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV32ZVFH %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
; RUN: llc -mtriple=riscv32 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV32ZIMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
Expand Down Expand Up @@ -186,7 +186,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/cmov-branch-opt.ll
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Expand Up @@ -3,13 +3,13 @@
; RUN: | FileCheck -check-prefix=NOCMOV %s
; RUN: llc -mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CMOV,CMOV-NOZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c,+experimental-zicond -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c,+zicond -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CMOV,CMOV-ZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-NOZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt,+c -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-NOZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt,+experimental-zicond -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt,+zicond -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-ZICOND %s

; The conditional move optimization in sifive-p450 requires that only a
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/condbinops.ll
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Expand Up @@ -3,8 +3,8 @@
; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS
; RUN: llc -mtriple=riscv64 -mattr=+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond < %s | FileCheck %s -check-prefix=RV64ZICOND
; RUN: llc -mtriple=riscv32 -mattr=+zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
; RUN: llc -mtriple=riscv64 -mattr=+zicond < %s | FileCheck %s -check-prefix=RV64ZICOND

define i32 @shl32(i32 %x, i32 %y, i1 %c) {
; RV32I-LABEL: shl32:
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/condops.ll
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Expand Up @@ -3,8 +3,8 @@
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs < %s | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV
; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs,+experimental-zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+experimental-zicond < %s | FileCheck %s -check-prefix=RV64ZICOND
; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs,+zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+zicond < %s | FileCheck %s -check-prefix=RV64ZICOND

define i64 @zero1(i64 %rs1, i1 zeroext %rc) {
; RV32I-LABEL: zero1:
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/select-binop-identity.ll
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Expand Up @@ -7,9 +7,9 @@
; RUN: | FileCheck -check-prefix=SFB64 %s
; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=VTCONDOPS64 %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv32 -mattr=+zicond -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32,ZICOND,ZICOND32 %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -mattr=+zicond -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=ZICOND,ZICOND64 %s

; InstCombine canonicalizes (c ? x | y : x) to (x | (c ? y : 0)) similar for
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/select.ll
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Expand Up @@ -2,8 +2,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV32IM %s
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64IM %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+xventanacondops -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64IMXVTCONDOPS %s
; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV32IMZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV64IMZICOND %s
; RUN: llc -mtriple=riscv32 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV32IMZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV64IMZICOND %s

define i16 @select_xor_1(i16 %A, i8 %cond) {
; RV32IM-LABEL: select_xor_1:
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
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Expand Up @@ -3,7 +3,7 @@
; RUN: | FileCheck -check-prefix=NOSFB %s
; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+zbb -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=SFB,NOZICOND,RV64SFB %s
; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+experimental-zicond,+zbb \
; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+zicond,+zbb \
; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=SFB,ZICOND %s
; RUN: llc -mtriple=riscv32 -mcpu=sifive-e76 -mattr=+zbb -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=SFB,NOZICOND,RV32SFB %s
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/xaluo.ll
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Expand Up @@ -3,8 +3,8 @@
; RUN: llc < %s -mtriple=riscv64 -mattr=+m -verify-machineinstrs | FileCheck %s --check-prefix=RV64
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zba -verify-machineinstrs | FileCheck %s --check-prefix=RV32ZBA
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zba -verify-machineinstrs | FileCheck %s --check-prefix=RV64ZBA
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zicond -verify-machineinstrs | FileCheck %s --check-prefix=RV32ZICOND
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zicond -verify-machineinstrs | FileCheck %s --check-prefix=RV64ZICOND
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zicond -verify-machineinstrs | FileCheck %s --check-prefix=RV32ZICOND
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zicond -verify-machineinstrs | FileCheck %s --check-prefix=RV64ZICOND

;
; Get the actual value of the overflow bit.
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4 changes: 2 additions & 2 deletions llvm/test/MC/RISCV/rv32zicond-invalid.s
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@@ -1,5 +1,5 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zicond < %s 2>&1 | FileCheck %s
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zicond < %s 2>&1 | FileCheck %s
# RUN: not llvm-mc -triple riscv32 -mattr=+zicond < %s 2>&1 | FileCheck %s
# RUN: not llvm-mc -triple riscv64 -mattr=+zicond < %s 2>&1 | FileCheck %s

# Use of operand modifier on register name
czero.eqz t1, %lo(t2), t3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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12 changes: 6 additions & 6 deletions llvm/test/MC/RISCV/rv32zicond-valid.s
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@@ -1,12 +1,12 @@
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicond -show-encoding \
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicond -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicond -show-encoding \
# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicond -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicond < %s \
# RUN: | llvm-objdump --mattr=+experimental-zicond -d -r - \
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicond < %s \
# RUN: | llvm-objdump --mattr=+zicond -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicond < %s \
# RUN: | llvm-objdump --mattr=+experimental-zicond -d -r - \
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zicond < %s \
# RUN: | llvm-objdump --mattr=+zicond -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s

# CHECK-ASM-AND-OBJ: czero.eqz t0, a3, ra
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