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[RISCV] Make Zcmt imply Zicsr. #75464

Merged
merged 1 commit into from
Dec 20, 2023
Merged

[RISCV] Make Zcmt imply Zicsr. #75464

merged 1 commit into from
Dec 20, 2023

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yroux
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@yroux yroux commented Dec 14, 2023

This patch fixes build attributes w/r to Zcmt extension dependency on Zicsr.

This patch fixes build attributes w/r to Zcmt extension dependency on
Zicsr.
@yroux yroux requested review from asb, topperc and Xinlong-Wu December 14, 2023 11:20
@llvmbot llvmbot added mc Machine (object) code llvm:support labels Dec 14, 2023
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llvmbot commented Dec 14, 2023

@llvm/pr-subscribers-llvm-support
@llvm/pr-subscribers-mc

@llvm/pr-subscribers-backend-risc-v

Author: None (yroux)

Changes

This patch fixes build attributes w/r to Zcmt extension dependency on Zicsr.


Full diff: https://github.com/llvm/llvm-project/pull/75464.diff

3 Files Affected:

  • (modified) llvm/lib/Support/RISCVISAInfo.cpp (+1-1)
  • (modified) llvm/test/MC/RISCV/attribute-arch.s (+1-1)
  • (modified) llvm/unittests/Support/RISCVISAInfoTest.cpp (+4-2)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 85c34dd6206307..5b06d790f83644 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -1006,7 +1006,7 @@ static const char *ImpliedExtsZcd[] = {"d", "zca"};
 static const char *ImpliedExtsZce[] = {"zcb", "zcmp", "zcmt"};
 static const char *ImpliedExtsZcf[] = {"f", "zca"};
 static const char *ImpliedExtsZcmp[] = {"zca"};
-static const char *ImpliedExtsZcmt[] = {"zca"};
+static const char *ImpliedExtsZcmt[] = {"zca", "zicsr"};
 static const char *ImpliedExtsZdinx[] = {"zfinx"};
 static const char *ImpliedExtsZfa[] = {"f"};
 static const char *ImpliedExtsZfbfmin[] = {"f"};
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 3ed48401e43fc8..66311c8c1e6df4 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -244,7 +244,7 @@
 # CHECK: attribute      5, "rv32i2p1_zca1p0_zcmp1p0"
 
 .attribute arch, "rv32izcmt1p0"
-# CHECK: attribute      5, "rv32i2p1_zca1p0_zcmt1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zca1p0_zcmt1p0"
 
 .attribute arch, "rv64i_xsfvcp"
 # CHECK: attribute      5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfvcp1p0"
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 3de14907899eb6..ef83c3f7ef6b24 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -519,8 +519,9 @@ TEST(ParseArchString, ZceImplication) {
   ASSERT_THAT_EXPECTED(MaybeRV32IZce, Succeeded());
   RISCVISAInfo::OrderedExtensionMap ExtsRV32IZce =
       (*MaybeRV32IZce)->getExtensions();
-  EXPECT_EQ(ExtsRV32IZce.size(), 6UL);
+  EXPECT_EQ(ExtsRV32IZce.size(), 7UL);
   EXPECT_EQ(ExtsRV32IZce.count("i"), 1U);
+  EXPECT_EQ(ExtsRV32IZce.count("zicsr"), 1U);
   EXPECT_EQ(ExtsRV32IZce.count("zca"), 1U);
   EXPECT_EQ(ExtsRV32IZce.count("zcb"), 1U);
   EXPECT_EQ(ExtsRV32IZce.count("zce"), 1U);
@@ -562,8 +563,9 @@ TEST(ParseArchString, ZceImplication) {
   ASSERT_THAT_EXPECTED(MaybeRV64IZce, Succeeded());
   RISCVISAInfo::OrderedExtensionMap ExtsRV64IZce =
       (*MaybeRV64IZce)->getExtensions();
-  EXPECT_EQ(ExtsRV64IZce.size(), 6UL);
+  EXPECT_EQ(ExtsRV64IZce.size(), 7UL);
   EXPECT_EQ(ExtsRV64IZce.count("i"), 1U);
+  EXPECT_EQ(ExtsRV64IZce.count("zicsr"), 1U);
   EXPECT_EQ(ExtsRV64IZce.count("zca"), 1U);
   EXPECT_EQ(ExtsRV64IZce.count("zcb"), 1U);
   EXPECT_EQ(ExtsRV64IZce.count("zce"), 1U);

@Xinlong-Wu
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Xinlong-Wu commented Dec 18, 2023

LGTM

But I'm curious why Zcmt depends on Zicsr, does register jvt need to be defined in Zicsr? Because I'm not familiar with Zicsr

@yroux
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yroux commented Dec 18, 2023

I'm not really familiar with Zicsr either, but yes it is written in the Zcmt JVT CSR description that:

If Zcmt is implemented then JVT must also be implemented, but can contain a read-only value.

which implies that Zicsr is required. The full discussion on the relationship between Zcmt and Zicsr is available in this issue:

riscvarchive/riscv-code-size-reduction#179

@yroux yroux requested a review from 4vtomat December 19, 2023 07:52
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LGTM

@yroux yroux merged commit 06d10d4 into llvm:main Dec 20, 2023
6 checks passed
@yroux yroux deleted the zcmt-zicsr branch December 20, 2023 08:48
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4 participants